mirror of
https://github.com/c64scene-ar/llvm-6502.git
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67a6b1c40c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186074 91177308-0d34-0410-b5e6-96231b3b80d8
267 lines
6.1 KiB
LLVM
267 lines
6.1 KiB
LLVM
; Test sequences that can use RISBG.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test an extraction of bit 0 from a right-shifted value.
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define i32 @f1(i32 %foo) {
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; CHECK: f1:
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; CHECK: risbg %r2, %r2, 63, 191, 54
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; CHECK: br %r14
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%shr = lshr i32 %foo, 10
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%and = and i32 %shr, 1
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f2(i64 %foo) {
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; CHECK: f2:
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; CHECK: risbg %r2, %r2, 63, 191, 54
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; CHECK: br %r14
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%shr = lshr i64 %foo, 10
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%and = and i64 %shr, 1
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ret i64 %and
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}
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; Test an extraction of other bits from a right-shifted value.
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define i32 @f3(i32 %foo) {
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; CHECK: f3:
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; CHECK: risbg %r2, %r2, 60, 189, 42
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; CHECK: br %r14
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%shr = lshr i32 %foo, 22
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%and = and i32 %shr, 12
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f4(i64 %foo) {
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; CHECK: f4:
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; CHECK: risbg %r2, %r2, 60, 189, 42
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; CHECK: br %r14
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%shr = lshr i64 %foo, 22
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%and = and i64 %shr, 12
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ret i64 %and
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}
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; Test an extraction of most bits from a right-shifted value.
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; The range should be reduced to exclude the zeroed high bits.
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define i32 @f5(i32 %foo) {
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; CHECK: f5:
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; CHECK: risbg %r2, %r2, 34, 188, 62
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; CHECK: br %r14
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%shr = lshr i32 %foo, 2
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%and = and i32 %shr, -8
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f6(i64 %foo) {
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; CHECK: f6:
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; CHECK: risbg %r2, %r2, 2, 188, 62
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; CHECK: br %r14
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%shr = lshr i64 %foo, 2
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%and = and i64 %shr, -8
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ret i64 %and
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}
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; Try the next value up (mask ....1111001). The mask itself is suitable
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; for RISBG, but the shift is still needed.
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define i32 @f7(i32 %foo) {
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; CHECK: f7:
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; CHECK: srl %r2, 2
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; CHECK: risbg %r2, %r2, 63, 188, 0
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; CHECK: br %r14
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%shr = lshr i32 %foo, 2
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%and = and i32 %shr, -7
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f8(i64 %foo) {
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; CHECK: f8:
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; CHECK: srlg [[REG:%r[0-5]]], %r2, 2
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; CHECK: risbg %r2, [[REG]], 63, 188, 0
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; CHECK: br %r14
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%shr = lshr i64 %foo, 2
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%and = and i64 %shr, -7
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ret i64 %and
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}
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; Test an extraction of bits from a left-shifted value. The range should
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; be reduced to exclude the zeroed low bits.
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define i32 @f9(i32 %foo) {
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; CHECK: f9:
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; CHECK: risbg %r2, %r2, 56, 189, 2
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; CHECK: br %r14
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%shr = shl i32 %foo, 2
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%and = and i32 %shr, 255
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f10(i64 %foo) {
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; CHECK: f10:
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; CHECK: risbg %r2, %r2, 56, 189, 2
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; CHECK: br %r14
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%shr = shl i64 %foo, 2
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%and = and i64 %shr, 255
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ret i64 %and
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}
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; Try a wrap-around mask (mask ....111100001111). The mask itself is suitable
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; for RISBG, but the shift is still needed.
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define i32 @f11(i32 %foo) {
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; CHECK: f11:
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; CHECK: sll %r2, 2
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; CHECK: risbg %r2, %r2, 60, 183, 0
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; CHECK: br %r14
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%shr = shl i32 %foo, 2
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%and = and i32 %shr, -241
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f12(i64 %foo) {
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; CHECK: f12:
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; CHECK: sllg [[REG:%r[0-5]]], %r2, 2
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; CHECK: risbg %r2, [[REG]], 60, 183, 0
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; CHECK: br %r14
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%shr = shl i64 %foo, 2
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%and = and i64 %shr, -241
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ret i64 %and
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}
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; Test an extraction from a rotated value, no mask wraparound.
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; This is equivalent to the lshr case, because the bits from the
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; shl are not used.
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define i32 @f13(i32 %foo) {
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; CHECK: f13:
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; CHECK: risbg %r2, %r2, 56, 188, 46
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; CHECK: br %r14
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%parta = shl i32 %foo, 14
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%partb = lshr i32 %foo, 18
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%rotl = or i32 %parta, %partb
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%and = and i32 %rotl, 248
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f14(i64 %foo) {
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; CHECK: f14:
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; CHECK: risbg %r2, %r2, 56, 188, 14
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; CHECK: br %r14
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%parta = shl i64 %foo, 14
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%partb = lshr i64 %foo, 50
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%rotl = or i64 %parta, %partb
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%and = and i64 %rotl, 248
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ret i64 %and
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}
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; Try a case in which only the bits from the shl are used.
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define i32 @f15(i32 %foo) {
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; CHECK: f15:
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; CHECK: risbg %r2, %r2, 47, 177, 14
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; CHECK: br %r14
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%parta = shl i32 %foo, 14
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%partb = lshr i32 %foo, 18
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%rotl = or i32 %parta, %partb
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%and = and i32 %rotl, 114688
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f16(i64 %foo) {
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; CHECK: f16:
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; CHECK: risbg %r2, %r2, 47, 177, 14
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; CHECK: br %r14
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%parta = shl i64 %foo, 14
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%partb = lshr i64 %foo, 50
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%rotl = or i64 %parta, %partb
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%and = and i64 %rotl, 114688
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ret i64 %and
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}
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; Test a 32-bit rotate in which both parts of the OR are needed.
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; This needs a separate shift (although RISBLG would be better
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; if supported).
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define i32 @f17(i32 %foo) {
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; CHECK: f17:
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; CHECK: rll [[REG:%r[0-5]]], %r2, 4
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; CHECK: risbg %r2, [[REG]], 57, 190, 0
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; CHECK: br %r14
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%parta = shl i32 %foo, 4
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%partb = lshr i32 %foo, 28
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%rotl = or i32 %parta, %partb
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%and = and i32 %rotl, 126
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ret i32 %and
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}
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; ...and for i64, where RISBG should do the rotate too.
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define i64 @f18(i64 %foo) {
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; CHECK: f18:
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; CHECK: risbg %r2, %r2, 57, 190, 4
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; CHECK: br %r14
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%parta = shl i64 %foo, 4
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%partb = lshr i64 %foo, 60
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%rotl = or i64 %parta, %partb
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%and = and i64 %rotl, 126
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ret i64 %and
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}
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; Test an arithmetic shift right in which some of the sign bits are kept.
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; The SRA is still needed.
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define i32 @f19(i32 %foo) {
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; CHECK: f19:
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; CHECK: sra %r2, 28
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; CHECK: risbg %r2, %r2, 59, 190, 0
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; CHECK: br %r14
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%shr = ashr i32 %foo, 28
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%and = and i32 %shr, 30
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f20(i64 %foo) {
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; CHECK: f20:
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; CHECK: srag [[REG:%r[0-5]]], %r2, 60
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; CHECK: risbg %r2, [[REG]], 59, 190, 0
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; CHECK: br %r14
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%shr = ashr i64 %foo, 60
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%and = and i64 %shr, 30
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ret i64 %and
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}
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; Now try an arithmetic right shift in which the sign bits aren't needed.
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; Introduce a second use of %shr so that the ashr doesn't decompose to
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; an lshr.
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define i32 @f21(i32 %foo, i32 *%dest) {
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; CHECK: f21:
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; CHECK: risbg %r2, %r2, 60, 190, 36
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; CHECK: br %r14
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%shr = ashr i32 %foo, 28
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store i32 %shr, i32 *%dest
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%and = and i32 %shr, 14
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f22(i64 %foo, i64 *%dest) {
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; CHECK: f22:
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; CHECK: risbg %r2, %r2, 60, 190, 4
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; CHECK: br %r14
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%shr = ashr i64 %foo, 60
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store i64 %shr, i64 *%dest
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%and = and i64 %shr, 14
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ret i64 %and
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}
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; Check that we use RISBG for shifted values even if the AND is a
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; natural zero extension.
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define i64 @f23(i64 %foo) {
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; CHECK: f23:
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; CHECK: risbg %r2, %r2, 56, 191, 62
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; CHECK: br %r14
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%shr = lshr i64 %foo, 2
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%and = and i64 %shr, 255
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ret i64 %and
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}
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