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https://github.com/c64scene-ar/llvm-6502.git
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ca795b61be
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
2.7 KiB
LLVM
88 lines
2.7 KiB
LLVM
; Test the MSA intrinsics that are encoded with the 2R instruction format and
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; convert scalars to vectors.
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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@llvm_mips_fill_b_ARG1 = global i32 23, align 16
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@llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_fill_b_test() nounwind {
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entry:
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%0 = load i32* @llvm_mips_fill_b_ARG1
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%1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0)
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store <16 x i8> %1, <16 x i8>* @llvm_mips_fill_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
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; CHECK: llvm_mips_fill_b_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]],
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; CHECK-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
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; CHECK-DAG: st.b [[R2]],
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; CHECK: .size llvm_mips_fill_b_test
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;
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@llvm_mips_fill_h_ARG1 = global i32 23, align 16
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@llvm_mips_fill_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_fill_h_test() nounwind {
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entry:
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%0 = load i32* @llvm_mips_fill_h_ARG1
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%1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0)
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store <8 x i16> %1, <8 x i16>* @llvm_mips_fill_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
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; CHECK: llvm_mips_fill_h_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]],
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; CHECK-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
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; CHECK-DAG: st.h [[R2]],
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; CHECK: .size llvm_mips_fill_h_test
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;
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@llvm_mips_fill_w_ARG1 = global i32 23, align 16
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@llvm_mips_fill_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_fill_w_test() nounwind {
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entry:
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%0 = load i32* @llvm_mips_fill_w_ARG1
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%1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0)
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store <4 x i32> %1, <4 x i32>* @llvm_mips_fill_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
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; CHECK: llvm_mips_fill_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]],
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; CHECK-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
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; CHECK-DAG: st.w [[R2]],
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; CHECK: .size llvm_mips_fill_w_test
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;
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@llvm_mips_fill_d_ARG1 = global i64 23, align 16
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@llvm_mips_fill_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_fill_d_test() nounwind {
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entry:
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%0 = load i64* @llvm_mips_fill_d_ARG1
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%1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)
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store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.fill.d(i64) nounwind
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; CHECK: llvm_mips_fill_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
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; CHECK-DAG: lw [[R2:\$[0-9]+]], 4(
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; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 0
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; CHECK-DAG: insert.w [[R3]][0], [[R1]]
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; CHECK-DAG: insert.w [[R3]][1], [[R2]]
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; CHECK-DAG: insert.w [[R3]][2], [[R1]]
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; CHECK-DAG: insert.w [[R3]][3], [[R2]]
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; CHECK-DAG: st.w [[R3]],
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; CHECK: .size llvm_mips_fill_d_test
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;
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