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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
727 B
LLVM
31 lines
727 B
LLVM
; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 < %s
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; rdar://10196296
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; ARM target specific dag combine created a cycle in DAG.
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define void @t() nounwind ssp {
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%1 = load i64, i64* undef, align 4
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%2 = shl i32 5, 0
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%3 = zext i32 %2 to i64
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%4 = and i64 %1, %3
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%5 = lshr i64 %4, undef
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switch i64 %5, label %8 [
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i64 0, label %9
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i64 1, label %6
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i64 4, label %9
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i64 5, label %7
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]
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; <label>:6 ; preds = %0
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unreachable
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; <label>:7 ; preds = %0
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unreachable
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; <label>:8 ; preds = %0
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unreachable
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; <label>:9 ; preds = %0, %0
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ret void
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}
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