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42deb12738
This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214460 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
947 B
TableGen
25 lines
947 B
TableGen
//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel SGX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SGX instructions
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// ENCLS - Execute an Enclave System Function of Specified Leaf Number
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def ENCLS : I<0x01, MRM_CF, (outs), (ins),
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"encls", []>, TB, Requires<[HasSGX]>;
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// ENCLU - Execute an Enclave User Function of Specified Leaf Number
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def ENCLU : I<0x01, MRM_D7, (outs), (ins),
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"enclu", []>, TB, Requires<[HasSGX]>;
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