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https://github.com/c64scene-ar/llvm-6502.git
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ab5b9489e9
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198760 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.3 KiB
ArmAsm
49 lines
1.3 KiB
ArmAsm
// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
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// RUN: FileCheck --check-prefix=64 < %t.err %s
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// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
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// RUN: FileCheck --check-prefix=32 < %t.err %s
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// rdar://8204588
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// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
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cmp $0, 0(%eax)
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// 32: error: register %rax is only available in 64-bit mode
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addl $0, 0(%rax)
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// 32: test.s:8:2: error: invalid instruction mnemonic 'movi'
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# 8 "test.s"
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movi $8,%eax
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movl 0(%rax), 0(%edx) // error: invalid operand for instruction
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// 32: error: instruction requires: 64-bit mode
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sysexitq
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// rdar://10710167
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// 64: error: expected scale expression
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lea (%rsp, %rbp, $4), %rax
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// rdar://10423777
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// 64: error: base register is 64-bit, but index register is not
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movq (%rsi,%ecx),%xmm0
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// 64: error: invalid 16-bit base register
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movl %eax,(%bp,%si)
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// 32: error: scale factor in 16-bit address must be 1
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movl %eax,(%bp,%si,2)
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// 32: error: invalid 16-bit base register
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movl %eax,(%cx)
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// 32: error: invalid 16-bit base/index register combination
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movl %eax,(%bp,%bx)
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// 32: error: 16-bit memory operand may not include only index register
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movl %eax,(,%bx)
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// 32: error: invalid operand for instruction
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outb al, 4
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