mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-06 05:06:45 +00:00
cd799b99cb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
401 lines
14 KiB
TableGen
401 lines
14 KiB
TableGen
//===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM VFP instruction set.
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//
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//===----------------------------------------------------------------------===//
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def SDT_FTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDT_ITOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SDT_CMPFP0 :
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SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def SDT_FMDRR :
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SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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//
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let canFoldAsLoad = 1 in {
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def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
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"fldd", " $dst, $addr",
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[(set DPR:$dst, (load addrmode5:$addr))]>;
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def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
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"flds", " $dst, $addr",
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[(set SPR:$dst, (load addrmode5:$addr))]>;
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} // canFoldAsLoad
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def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
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"fstd", " $src, $addr",
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[(store DPR:$src, addrmode5:$addr)]>;
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def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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"fsts", " $src, $addr",
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[(store SPR:$src, addrmode5:$addr)]>;
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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let mayLoad = 1 in {
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def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
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variable_ops),
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"fldm${addr:submode}d${p} ${addr:base}, $dst1",
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[]> {
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let Inst{20} = 1;
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}
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def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
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variable_ops),
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"fldm${addr:submode}s${p} ${addr:base}, $dst1",
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[]> {
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let Inst{20} = 1;
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}
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}
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let mayStore = 1 in {
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def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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variable_ops),
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"fstm${addr:submode}d${p} ${addr:base}, $src1",
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[]> {
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let Inst{20} = 0;
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}
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def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
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variable_ops),
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"fstm${addr:submode}s${p} ${addr:base}, $src1",
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[]> {
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let Inst{20} = 0;
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}
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} // mayStore
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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//===----------------------------------------------------------------------===//
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// FP Binary Operations.
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//
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def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"faddd", " $dst, $a, $b",
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[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
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def FADDS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fadds", " $dst, $a, $b",
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[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
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// These are encoded as unary instructions.
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def FCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b),
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"fcmped", " $a, $b",
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[(arm_cmpfp DPR:$a, DPR:$b)]>;
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def FCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b),
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"fcmpes", " $a, $b",
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[(arm_cmpfp SPR:$a, SPR:$b)]>;
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def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fdivd", " $dst, $a, $b",
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[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
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def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fdivs", " $dst, $a, $b",
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[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
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def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fmuld", " $dst, $a, $b",
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[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
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def FMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fmuls", " $dst, $a, $b",
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[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
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def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fnmuld", " $dst, $a, $b",
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[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
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let Inst{6} = 1;
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}
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def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fnmuls", " $dst, $a, $b",
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[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
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let Inst{6} = 1;
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}
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// Match reassociated forms only if not sign dependent rounding.
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def : Pat<(fmul (fneg DPR:$a), DPR:$b),
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(FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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def : Pat<(fmul (fneg SPR:$a), SPR:$b),
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(FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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"fsubd", " $dst, $a, $b",
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[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
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let Inst{6} = 1;
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}
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def FSUBS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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"fsubs", " $dst, $a, $b",
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[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
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let Inst{6} = 1;
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}
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//===----------------------------------------------------------------------===//
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// FP Unary Operations.
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//
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def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
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"fabsd", " $dst, $a",
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[(set DPR:$dst, (fabs DPR:$a))]>;
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def FABSS : ASuI<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
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"fabss", " $dst, $a",
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[(set SPR:$dst, (fabs SPR:$a))]>;
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def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
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"fcmpezd", " $a",
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[(arm_cmpfp0 DPR:$a)]>;
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def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
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"fcmpezs", " $a",
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[(arm_cmpfp0 SPR:$a)]>;
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def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
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"fcvtds", " $dst, $a",
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[(set DPR:$dst, (fextend SPR:$a))]>;
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// Special case encoding: bits 11-8 is 0b1011.
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def FCVTSD : AI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
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"fcvtsd", " $dst, $a",
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[(set SPR:$dst, (fround DPR:$a))]> {
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let Inst{27-23} = 0b11101;
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let Inst{21-16} = 0b110111;
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let Inst{11-8} = 0b1011;
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let Inst{7-4} = 0b1100;
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}
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let neverHasSideEffects = 1 in {
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def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
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"fcpyd", " $dst, $a", []>;
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def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
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"fcpys", " $dst, $a", []>;
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} // neverHasSideEffects
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def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
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"fnegd", " $dst, $a",
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[(set DPR:$dst, (fneg DPR:$a))]>;
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def FNEGS : ASuI<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
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"fnegs", " $dst, $a",
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[(set SPR:$dst, (fneg SPR:$a))]>;
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def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
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"fsqrtd", " $dst, $a",
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[(set DPR:$dst, (fsqrt DPR:$a))]>;
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def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
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"fsqrts", " $dst, $a",
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[(set SPR:$dst, (fsqrt SPR:$a))]>;
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//===----------------------------------------------------------------------===//
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// FP <-> GPR Copies. Int <-> FP Conversions.
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//
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def FMRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
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"fmrs", " $dst, $src",
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[(set GPR:$dst, (bitconvert SPR:$src))]>;
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def FMSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
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"fmsr", " $dst, $src",
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[(set SPR:$dst, (bitconvert GPR:$src))]>;
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def FMRRD : AVConv3I<0b11000101, 0b1011,
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(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
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"fmrrd", " $dst1, $dst2, $src",
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[/* FIXME: Can't write pattern for multiple result instr*/]>;
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// FMDHR: GPR -> SPR
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// FMDLR: GPR -> SPR
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def FMDRR : AVConv5I<0b11000100, 0b1011,
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(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
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"fmdrr", " $dst, $src1, $src2",
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[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
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// FMRDH: SPR -> GPR
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// FMRDL: SPR -> GPR
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// FMRRS: SPR -> GPR
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// FMRX : SPR system reg -> GPR
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// FMSRR: GPR -> SPR
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// FMXR: GPR -> VFP Sstem reg
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// Int to FP:
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def FSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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"fsitod", " $dst, $a",
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[(set DPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1;
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}
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def FSITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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"fsitos", " $dst, $a",
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[(set SPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1;
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}
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def FUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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"fuitod", " $dst, $a",
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[(set DPR:$dst, (arm_uitof SPR:$a))]>;
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def FUITOS : AVConv1I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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"fuitos", " $dst, $a",
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[(set SPR:$dst, (arm_uitof SPR:$a))]>;
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// FP to Int:
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// Always set Z bit in the instruction, i.e. "round towards zero" variants.
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def FTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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"ftosizd", " $dst, $a",
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[(set SPR:$dst, (arm_ftosi DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOSIZS : AVConv1I<0b11101011, 0b1101, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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"ftosizs", " $dst, $a",
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[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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"ftouizd", " $dst, $a",
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[(set SPR:$dst, (arm_ftoui DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOUIZS : AVConv1I<0b11101011, 0b1100, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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"ftouizs", " $dst, $a",
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[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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//===----------------------------------------------------------------------===//
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// FP FMA Operations.
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//
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def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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"fmacd", " $dst, $a, $b",
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[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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"fmacs", " $dst, $a, $b",
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[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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"fmscd", " $dst, $a, $b",
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[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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"fmscs", " $dst, $a, $b",
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[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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"fnmacd", " $dst, $a, $b",
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[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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}
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def FNMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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"fnmacs", " $dst, $a, $b",
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[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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}
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def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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"fnmscd", " $dst, $a, $b",
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[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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}
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def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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"fnmscs", " $dst, $a, $b",
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[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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}
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//===----------------------------------------------------------------------===//
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// FP Conditional moves.
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//
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def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100,
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(outs DPR:$dst), (ins DPR:$false, DPR:$true),
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"fcpyd", " $dst, $true",
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[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100,
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(outs SPR:$dst), (ins SPR:$false, SPR:$true),
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"fcpys", " $dst, $true",
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[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
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(outs DPR:$dst), (ins DPR:$false, DPR:$true),
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"fnegd", " $dst, $true",
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[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
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(outs SPR:$dst), (ins SPR:$false, SPR:$true),
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"fnegs", " $dst, $true",
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[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
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RegConstraint<"$false = $dst">;
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//===----------------------------------------------------------------------===//
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// Misc.
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//
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let Defs = [CPSR] in
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def FMSTAT : AI<(outs), (ins), VFPMiscFrm, "fmstat", "", [(arm_fmstat)]> {
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let Inst{27-20} = 0b11101111;
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let Inst{19-16} = 0b0001;
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let Inst{15-12} = 0b1111;
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let Inst{11-8} = 0b1010;
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let Inst{7} = 0;
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let Inst{4} = 1;
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}
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