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514d703ff6
for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203125 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
2.4 KiB
C++
84 lines
2.4 KiB
C++
//==-- AArch64Subtarget.h - Define Subtarget for the AArch64 ---*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_AARCH64_SUBTARGET_H
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#define LLVM_TARGET_AARCH64_SUBTARGET_H
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#include "llvm/ADT/Triple.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "AArch64GenSubtargetInfo.inc"
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#include <string>
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namespace llvm {
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class StringRef;
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class GlobalValue;
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class AArch64Subtarget : public AArch64GenSubtargetInfo {
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virtual void anchor();
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protected:
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enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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ARMProcFamilyEnum ARMProcFamily;
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bool HasFPARMv8;
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bool HasNEON;
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bool HasCrypto;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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/// CPUString - String name of used CPU.
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std::string CPUString;
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/// IsLittleEndian - The target is Little Endian
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bool IsLittleEndian;
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private:
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void initializeSubtargetFeatures(StringRef CPU, StringRef FS);
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
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bool LittleEndian);
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virtual bool enableMachineScheduler() const {
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return true;
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}
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool hasFPARMv8() const { return HasFPARMv8; }
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bool hasNEON() const { return HasNEON; }
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bool hasCrypto() const { return HasCrypto; }
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bool isLittle() const { return IsLittleEndian; }
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const std::string & getCPUString() const { return CPUString; }
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};
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} // End llvm namespace
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#endif // LLVM_TARGET_AARCH64_SUBTARGET_H
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