llvm-6502/test/CodeGen/Mips/cconv
Zoran Jovanovic fc6a659676 [mips] Emit two CFI offset directives per double precision SDC1/LDC1
instead of just one for FR=1 registers
Differential Revision: http://reviews.llvm.org/D4310


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212769 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 22:23:30 +00:00
..
arguments-float.ll
arguments-fp128.ll
arguments-hard-float-varargs.ll
arguments-hard-float.ll
arguments-hard-fp128.ll
arguments.ll
callee-saved-float.ll
callee-saved-fpxx1.ll [mips] Added FPXX modeless calling convention. 2014-07-10 15:36:12 +00:00
callee-saved-fpxx.ll [mips] Added FPXX modeless calling convention. 2014-07-10 15:36:12 +00:00
callee-saved.ll
memory-layout.ll
reserved-space.ll
return-float.ll [mips] Correct r206370 to account for non-Linux targets using the small data section. 2014-04-16 12:29:08 +00:00
return-hard-float.ll [mips] Emit two CFI offset directives per double precision SDC1/LDC1 2014-07-10 22:23:30 +00:00
return-hard-fp128.ll
return.ll [mips] Correct r206370 to account for non-Linux targets using the small data section. 2014-04-16 12:29:08 +00:00
stack-alignment.ll