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llvm-6502/test/CodeGen
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Evan Cheng 5adb66a646 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 09:14:39 +00:00
..
Alpha
ARM Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of 2009-09-28 05:28:43 +00:00
Blackfin Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of 2009-09-28 05:28:43 +00:00
CBackend
CellSPU
CPP
Generic
Mips
MSP430
PIC16
PowerPC
SPARC
SystemZ
Thumb
Thumb2 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 2009-09-28 09:14:39 +00:00
X86 Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of 2009-09-28 05:28:43 +00:00
XCore