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This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
3.8 KiB
LLVM
104 lines
3.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -enable-misched < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}frem_f32:
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; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}}
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; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
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; SI-DAG: v_cmp
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; SI-DAG: v_mul_f32
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; SI: v_rcp_f32_e32
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; SI: v_mul_f32_e32
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; SI: v_mul_f32_e32
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; SI: v_trunc_f32_e32
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; SI: v_mad_f32
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; SI: s_endpgm
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define void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #0 {
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%gep2 = getelementptr float addrspace(1)* %in2, i32 4
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%r0 = load float addrspace(1)* %in1, align 4
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%r1 = load float addrspace(1)* %gep2, align 4
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%r2 = frem float %r0, %r1
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store float %r2, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_frem_f32:
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; SI: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16
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; SI: buffer_load_dword [[X:v[0-9]+]], {{.*}}
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; SI: v_rcp_f32_e32 [[INVY:v[0-9]+]], [[Y]]
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; SI: v_mul_f32_e32 [[DIV:v[0-9]+]], [[INVY]], [[X]]
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; SI: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[DIV]]
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; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[TRUNC]], [[Y]], [[X]]
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2) #1 {
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%gep2 = getelementptr float addrspace(1)* %in2, i32 4
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%r0 = load float addrspace(1)* %in1, align 4
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%r1 = load float addrspace(1)* %gep2, align 4
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%r2 = frem float %r0, %r1
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store float %r2, float addrspace(1)* %out, align 4
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ret void
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}
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; TODO: This should check something when f64 fdiv is implemented
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; correctly
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; FUNC-LABEL: {{^}}frem_f64:
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; SI: s_endpgm
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define void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%r0 = load double addrspace(1)* %in1, align 8
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%r1 = load double addrspace(1)* %in2, align 8
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%r2 = frem double %r0, %r1
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store double %r2, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_frem_f64:
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; SI: v_rcp_f64_e32
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; SI: v_mul_f64
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; SI: v_bfe_u32
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; SI: v_fma_f64
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; SI: s_endpgm
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define void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) #1 {
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%r0 = load double addrspace(1)* %in1, align 8
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%r1 = load double addrspace(1)* %in2, align 8
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%r2 = frem double %r0, %r1
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store double %r2, double addrspace(1)* %out, align 8
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ret void
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}
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define void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
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<2 x float> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <2 x float> addrspace(1)* %in2, i32 4
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%r0 = load <2 x float> addrspace(1)* %in1, align 8
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%r1 = load <2 x float> addrspace(1)* %gep2, align 8
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%r2 = frem <2 x float> %r0, %r1
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store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
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ret void
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}
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define void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
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<4 x float> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <4 x float> addrspace(1)* %in2, i32 4
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%r0 = load <4 x float> addrspace(1)* %in1, align 16
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%r1 = load <4 x float> addrspace(1)* %gep2, align 16
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%r2 = frem <4 x float> %r0, %r1
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store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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define void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
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<2 x double> addrspace(1)* %in2) #0 {
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%gep2 = getelementptr <2 x double> addrspace(1)* %in2, i32 4
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%r0 = load <2 x double> addrspace(1)* %in1, align 16
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%r1 = load <2 x double> addrspace(1)* %gep2, align 16
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%r2 = frem <2 x double> %r0, %r1
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store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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attributes #0 = { nounwind "unsafe-fp-math"="false" }
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attributes #1 = { nounwind "unsafe-fp-math"="true" }
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