Andrew Trick 5469976506 Added a check in the preRA scheduler for potential interference on a ...

induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8

2011-04-07 19:54:57 +00:00

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Alpha

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ARM

Added a check in the preRA scheduler for potential interference on a

2011-04-07 19:54:57 +00:00

Blackfin

Don't completely eliminate identity copies that also modify super register liveness.

2011-03-31 17:55:25 +00:00

CBackend

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CellSPU

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CPP

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Generic

ARM doesn't support byval yet. XFAIL this test until it does.

2011-04-05 17:16:21 +00:00

MBlaze

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Mips

Fix handling of functions with internal linkage.

2011-04-07 19:51:44 +00:00

MSP430

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PowerPC

These tests no longer require linear scan because reserved register coalescing is now universal.

2011-04-05 21:40:41 +00:00

PTX

ptx: support setp's 4-operand format

2011-04-02 08:51:39 +00:00

SPARC

These tests no longer require linear scan because reserved register coalescing is now universal.

2011-04-05 21:40:41 +00:00

SystemZ

Fix SystemZ tests

2011-03-31 23:02:12 +00:00

Thumb

Fix Thumb and Thumb2 tests to be register allocator independent.

2011-03-31 23:31:50 +00:00

Thumb2

Fix Thumb and Thumb2 tests to be register allocator independent.

2011-03-31 23:31:50 +00:00

X86

Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.

2011-04-05 21:40:37 +00:00

XCore

Fix Mips, Sparc, and XCore tests that were dependent on register allocation.

2011-03-31 18:42:43 +00:00