Andrew Trick 5469976506 Added a check in the preRA scheduler for potential interference on a ... induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-07 19:54:57 +00:00
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Alpha
ARM	Added a check in the preRA scheduler for potential interference on a	2011-04-07 19:54:57 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic	ARM doesn't support byval yet. XFAIL this test until it does.	2011-04-05 17:16:21 +00:00
MBlaze
Mips	Fix handling of functions with internal linkage.	2011-04-07 19:51:44 +00:00
MSP430
PowerPC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
PTX	ptx: support setp's 4-operand format	2011-04-02 08:51:39 +00:00
SPARC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
SystemZ
Thumb
Thumb2
X86	Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.	2011-04-05 21:40:37 +00:00
XCore