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https://github.com/c64scene-ar/llvm-6502.git
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5494792536
We were incorrectly assuming that all VOP2 instructions can read SGPRs in Src0, but this is not true for instructions that read carry-in from VCC. The old logic has been replaced with new logic which checks the defined register classes of the VOP2 instruction to determine whether or not to legalize the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214465 91177308-0d34-0410-b5e6-96231b3b80d8
223 lines
8.7 KiB
C++
223 lines
8.7 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIINSTRINFO_H
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#define SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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const TargetRegisterClass *RC,
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const MachineOperand &Op) const;
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void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst, unsigned Opcode) const;
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void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst, unsigned Opcode) const;
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void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst) const;
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void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
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public:
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explicit SIInstrInfo(const AMDGPUSubtarget &st);
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const SIRegisterInfo &getRegisterInfo() const override {
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return RI;
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}
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bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
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unsigned &BaseReg, unsigned &Offset,
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const TargetRegisterInfo *TRI) const final;
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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unsigned commuteOpcode(unsigned Opcode) const;
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MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI=false) const override;
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bool isTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA = nullptr) const;
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MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg) const override;
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bool isMov(unsigned Opcode) const override;
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
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bool isDS(uint16_t Opcode) const;
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bool isMIMG(uint16_t Opcode) const;
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bool isSMRD(uint16_t Opcode) const;
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bool isMUBUF(uint16_t Opcode) const;
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bool isMTBUF(uint16_t Opcode) const;
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bool isVOP1(uint16_t Opcode) const;
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bool isVOP2(uint16_t Opcode) const;
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bool isVOP3(uint16_t Opcode) const;
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bool isVOPC(uint16_t Opcode) const;
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bool isInlineConstant(const APInt &Imm) const;
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bool isInlineConstant(const MachineOperand &MO) const;
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bool isLiteralConstant(const MachineOperand &MO) const;
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bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
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const MachineOperand &MO) const;
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/// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
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/// This function will return false if you pass it a 32-bit instruction.
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bool hasVALU32BitEncoding(unsigned Opcode) const;
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bool verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const override;
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bool isSALUInstr(const MachineInstr &MI) const;
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static unsigned getVALUOp(const MachineInstr &MI);
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bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
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/// \brief Return the correct register class for \p OpNo. For target-specific
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/// instructions, this will return the register class that has been defined
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/// in tablegen. For generic instructions, like REG_SEQUENCE it will return
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/// the register class of its machine operand.
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/// to infer the correct register class base on the other operands.
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const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
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unsigned OpNo) const;\
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/// \returns true if it is legal for the operand at index \p OpNo
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/// to read a VGPR.
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bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
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/// \brief Legalize the \p OpIndex operand of this instruction by inserting
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/// a MOV. For example:
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/// ADD_I32_e32 VGPR0, 15
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/// to
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/// MOV VGPR1, 15
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/// ADD_I32_e32 VGPR0, VGPR1
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///
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/// If the operand being legalized is a register, then a COPY will be used
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/// instead of MOV.
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void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
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/// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
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/// for \p MI.
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bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
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const MachineOperand *MO = nullptr) const;
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/// \brief Legalize all operands in this instruction. This function may
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/// create new instruction and insert them before \p MI.
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void legalizeOperands(MachineInstr *MI) const;
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void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
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/// \brief Replace this instruction's opcode with the equivalent VALU
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/// opcode. This function will also move the users of \p MI to the
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/// VALU if necessary.
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void moveToVALU(MachineInstr &MI) const;
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unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const override;
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const TargetRegisterClass *getIndirectAddrRegClass() const override;
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MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const override;
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MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const override;
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void reserveIndirectRegisters(BitVector &Reserved,
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const MachineFunction &MF) const;
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void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
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unsigned SavReg, unsigned IndexReg) const;
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void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
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/// \brief Returns the operand named \p Op. If \p MI does not have an
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/// operand named \c Op, this function returns nullptr.
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MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
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};
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namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getVOPe32(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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int getMCOpcode(uint16_t Opcode, unsigned Gen);
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const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
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const uint64_t RSRC_TID_ENABLE = 1LL << 55;
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} // End namespace AMDGPU
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} // End namespace llvm
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 0,
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EXP_CNT = 1 << 1,
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LGKM_CNT = 1 << 2
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};
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}
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#endif //SIINSTRINFO_H
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