mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
4.6 KiB
LLVM
139 lines
4.6 KiB
LLVM
; RUN: llc < %s -mattr=+sha -mtriple=x86_64-unknown-unknown | FileCheck %s
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; RUN: not llc < %s -mtriple=x86_64-unknown-unknown
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declare <4 x i32> @llvm.x86.sha1rnds4(<4 x i32>, <4 x i32>, i8) nounwind readnone
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define <4 x i32> @test_sha1rnds4rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %b, i8 3)
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ret <4 x i32> %0
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; CHECK: test_sha1rnds4rr
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; CHECK: sha1rnds4 $3, %xmm1, %xmm0
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}
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define <4 x i32> @test_sha1rnds4rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %b
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%1 = tail call <4 x i32> @llvm.x86.sha1rnds4(<4 x i32> %a, <4 x i32> %0, i8 3)
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ret <4 x i32> %1
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; CHECK: test_sha1rnds4rm
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; CHECK: sha1rnds4 $3, (%rdi), %xmm0
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}
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declare <4 x i32> @llvm.x86.sha1nexte(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_sha1nexterr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK: test_sha1nexterr
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; CHECK: sha1nexte %xmm1, %xmm0
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}
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define <4 x i32> @test_sha1nexterm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %b
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%1 = tail call <4 x i32> @llvm.x86.sha1nexte(<4 x i32> %a, <4 x i32> %0)
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ret <4 x i32> %1
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; CHECK: test_sha1nexterm
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; CHECK: sha1nexte (%rdi), %xmm0
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}
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declare <4 x i32> @llvm.x86.sha1msg1(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_sha1msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK: test_sha1msg1rr
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; CHECK: sha1msg1 %xmm1, %xmm0
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}
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define <4 x i32> @test_sha1msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %b
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%1 = tail call <4 x i32> @llvm.x86.sha1msg1(<4 x i32> %a, <4 x i32> %0)
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ret <4 x i32> %1
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; CHECK: test_sha1msg1rm
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; CHECK: sha1msg1 (%rdi), %xmm0
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}
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declare <4 x i32> @llvm.x86.sha1msg2(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_sha1msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK: test_sha1msg2rr
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; CHECK: sha1msg2 %xmm1, %xmm0
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}
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define <4 x i32> @test_sha1msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %b
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%1 = tail call <4 x i32> @llvm.x86.sha1msg2(<4 x i32> %a, <4 x i32> %0)
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ret <4 x i32> %1
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; CHECK: test_sha1msg2rm
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; CHECK: sha1msg2 (%rdi), %xmm0
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}
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declare <4 x i32> @llvm.x86.sha256rnds2(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_sha256rnds2rr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind uwtable {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
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ret <4 x i32> %0
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; CHECK: test_sha256rnds2rr
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; CHECK: movaps %xmm0, [[XMM_TMP1:%xmm[1-9][0-9]?]]
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; CHECK: movaps %xmm2, %xmm0
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; CHECK: sha256rnds2 %xmm1, [[XMM_TMP1]]
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}
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define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %b
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%1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c)
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ret <4 x i32> %1
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; CHECK: test_sha256rnds2rm
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; CHECK: movaps %xmm0, [[XMM_TMP2:%xmm[1-9][0-9]?]]
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; CHECK: movaps %xmm1, %xmm0
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; CHECK: sha256rnds2 (%rdi), [[XMM_TMP2]]
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}
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declare <4 x i32> @llvm.x86.sha256msg1(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_sha256msg1rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK: test_sha256msg1rr
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; CHECK: sha256msg1 %xmm1, %xmm0
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}
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define <4 x i32> @test_sha256msg1rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %b
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%1 = tail call <4 x i32> @llvm.x86.sha256msg1(<4 x i32> %a, <4 x i32> %0)
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ret <4 x i32> %1
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; CHECK: test_sha256msg1rm
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; CHECK: sha256msg1 (%rdi), %xmm0
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}
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declare <4 x i32> @llvm.x86.sha256msg2(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @test_sha256msg2rr(<4 x i32> %a, <4 x i32> %b) nounwind uwtable {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK: test_sha256msg2rr
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; CHECK: sha256msg2 %xmm1, %xmm0
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}
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define <4 x i32> @test_sha256msg2rm(<4 x i32> %a, <4 x i32>* %b) nounwind uwtable {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %b
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%1 = tail call <4 x i32> @llvm.x86.sha256msg2(<4 x i32> %a, <4 x i32> %0)
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ret <4 x i32> %1
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; CHECK: test_sha256msg2rm
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; CHECK: sha256msg2 (%rdi), %xmm0
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} |