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https://github.com/c64scene-ar/llvm-6502.git
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fcd3c4065d
than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227102 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
4.3 KiB
LLVM
160 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32
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@c = common global i8 0, align 4
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@s = common global i16 0, align 4
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@i = common global i32 0, align 4
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@l = common global i64 0, align 8
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@uc = common global i8 0, align 4
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@us = common global i16 0, align 4
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@ui = common global i32 0, align 4
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@l1 = common global i64 0, align 8
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define i64 @func1() nounwind readonly {
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entry:
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; CHECK-N64: func1
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N64: lb ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func1
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]])
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%0 = load i8* @c, align 4
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%conv = sext i8 %0 to i64
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ret i64 %conv
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}
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define i64 @func2() nounwind readonly {
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entry:
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; CHECK-N64: func2
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N64: lh ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func2
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]])
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%0 = load i16* @s, align 4
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%conv = sext i16 %0 to i64
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ret i64 %conv
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}
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define i64 @func3() nounwind readonly {
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entry:
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; CHECK-N64: func3
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N64: lw ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func3
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]])
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%0 = load i32* @i, align 4
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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define i64 @func4() nounwind readonly {
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entry:
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; CHECK-N64: func4
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N64: ld ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: func4
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64* @l, align 8
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ret i64 %0
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}
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define i64 @ufunc1() nounwind readonly {
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entry:
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; CHECK-N64: ufunc1
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(uc)
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; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: ufunc1
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(uc)
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; CHECK-N32: lbu ${{[0-9]+}}, 0($[[R0]])
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%0 = load i8* @uc, align 4
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%conv = zext i8 %0 to i64
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ret i64 %conv
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}
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define i64 @ufunc2() nounwind readonly {
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entry:
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; CHECK-N64: ufunc2
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(us)
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; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: ufunc2
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(us)
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; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]])
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%0 = load i16* @us, align 4
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%conv = zext i16 %0 to i64
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ret i64 %conv
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}
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define i64 @ufunc3() nounwind readonly {
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entry:
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; CHECK-N64: ufunc3
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(ui)
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; CHECK-N64: lwu ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: ufunc3
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(ui)
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; CHECK-N32: lwu ${{[0-9]+}}, 0($[[R0]])
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%0 = load i32* @ui, align 4
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%conv = zext i32 %0 to i64
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ret i64 %conv
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}
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define void @sfunc1() nounwind {
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entry:
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; CHECK-N64: sfunc1
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N64: sb ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc1
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(c)
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; CHECK-N32: sb ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64* @l1, align 8
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%conv = trunc i64 %0 to i8
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store i8 %conv, i8* @c, align 4
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ret void
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}
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define void @sfunc2() nounwind {
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entry:
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; CHECK-N64: sfunc2
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N64: sh ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc2
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(s)
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; CHECK-N32: sh ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64* @l1, align 8
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%conv = trunc i64 %0 to i16
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store i16 %conv, i16* @s, align 4
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ret void
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}
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define void @sfunc3() nounwind {
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entry:
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; CHECK-N64: sfunc3
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N64: sw ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc3
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(i)
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; CHECK-N32: sw ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64* @l1, align 8
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%conv = trunc i64 %0 to i32
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store i32 %conv, i32* @i, align 4
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ret void
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}
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define void @sfunc4() nounwind {
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entry:
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; CHECK-N64: sfunc4
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; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N64: sd ${{[0-9]+}}, 0($[[R0]])
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; CHECK-N32: sfunc4
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; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(l)
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; CHECK-N32: sd ${{[0-9]+}}, 0($[[R0]])
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%0 = load i64* @l1, align 8
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store i64 %0, i64* @l, align 8
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ret void
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}
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