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The mftb instruction was incorrectly marked as deprecated in the PPC Backend. Instead, it should not be treated as deprecated, but rather be implemented using the mfspr instruction. A similar patch was put into GCC last year. Details can be found at: https://sourceware.org/ml/binutils/2014-11/msg00383.html. This change will replace instances of the mftb instruction with the mfspr instruction for all CPUs except 601 and pwr3. This will also be the default behaviour. Additional details can be found in: https://llvm.org/bugs/show_bug.cgi?id=23680 Phabricator review: http://reviews.llvm.org/D10419 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239827 91177308-0d34-0410-b5e6-96231b3b80d8
215 lines
6.8 KiB
C++
215 lines
6.8 KiB
C++
//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCSubtarget.h"
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#include "PPC.h"
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#include "PPCRegisterInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cstdlib>
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using namespace llvm;
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#define DEBUG_TYPE "ppc-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "PPCGenSubtargetInfo.inc"
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static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
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cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
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static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
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cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
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cl::Hidden);
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PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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initializeEnvironment();
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initSubtargetFeatures(CPU, FS);
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return *this;
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}
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PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const PPCTargetMachine &TM)
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: PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
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IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
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TargetTriple.getArch() == Triple::ppc64le),
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TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
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InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
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void PPCSubtarget::initializeEnvironment() {
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StackAlignment = 16;
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DarwinDirective = PPC::DIR_NONE;
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HasMFOCRF = false;
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Has64BitSupport = false;
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Use64BitRegs = false;
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UseCRBits = false;
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HasAltivec = false;
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HasSPE = false;
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HasQPX = false;
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HasVSX = false;
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HasP8Vector = false;
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HasP8Altivec = false;
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HasP8Crypto = false;
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HasFCPSGN = false;
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HasFSQRT = false;
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HasFRE = false;
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HasFRES = false;
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HasFRSQRTE = false;
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HasFRSQRTES = false;
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HasRecipPrec = false;
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HasSTFIWX = false;
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HasLFIWAX = false;
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HasFPRND = false;
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HasFPCVT = false;
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HasISEL = false;
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HasPOPCNTD = false;
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HasBPERMD = false;
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HasExtDiv = false;
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HasCMPB = false;
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HasLDBRX = false;
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IsBookE = false;
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HasOnlyMSYNC = false;
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IsPPC4xx = false;
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IsPPC6xx = false;
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IsE500 = false;
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FeatureMFTB = false;
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DeprecatedDST = false;
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HasLazyResolverStubs = false;
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HasICBT = false;
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HasInvariantFunctionDescriptors = false;
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HasPartwordAtomics = false;
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HasDirectMove = false;
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IsQPXStackUnaligned = false;
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HasHTM = false;
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}
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void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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// Determine default and user specified characteristics
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std::string CPUName = CPU;
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if (CPUName.empty()) {
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// If cross-compiling with -march=ppc64le without -mcpu
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if (TargetTriple.getArch() == Triple::ppc64le)
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CPUName = "ppc64le";
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else
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CPUName = "generic";
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}
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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// If the user requested use of 64-bit regs, but the cpu selected doesn't
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// support it, ignore.
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if (IsPPC64 && has64BitSupport())
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Use64BitRegs = true;
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// Set up darwin-specific properties.
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if (isDarwin())
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HasLazyResolverStubs = true;
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// QPX requires a 32-byte aligned stack. Note that we need to do this if
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// we're compiling for a BG/Q system regardless of whether or not QPX
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// is enabled because external functions will assume this alignment.
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IsQPXStackUnaligned = QPXStackUnaligned;
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StackAlignment = getPlatformStackAlignment();
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// Determine endianness.
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// FIXME: Part of the TargetMachine.
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IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
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}
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/// hasLazyResolverStub - Return true if accesses to the specified global have
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/// to go through a dyld lazy resolution stub. This means that an extra load
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/// is required to get the address of the global.
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bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
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// We never have stubs if HasLazyResolverStubs=false or if in static mode.
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if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
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return false;
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bool isDecl = GV->isDeclaration();
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if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
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return false;
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return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
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GV->hasCommonLinkage() || isDecl;
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}
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// Embedded cores need aggressive scheduling (and some others also benefit).
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static bool needsAggressiveScheduling(unsigned Directive) {
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switch (Directive) {
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default: return false;
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case PPC::DIR_440:
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case PPC::DIR_A2:
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case PPC::DIR_E500mc:
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case PPC::DIR_E5500:
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case PPC::DIR_PWR7:
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case PPC::DIR_PWR8:
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return true;
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}
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}
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bool PPCSubtarget::enableMachineScheduler() const {
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// Enable MI scheduling for the embedded cores.
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// FIXME: Enable this for all cores (some additional modeling
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// may be necessary).
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return needsAggressiveScheduling(DarwinDirective);
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}
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// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
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bool PPCSubtarget::enablePostRAScheduler() const { return true; }
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PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
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return TargetSubtargetInfo::ANTIDEP_ALL;
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}
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void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(isPPC64() ?
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&PPC::G8RCRegClass : &PPC::GPRCRegClass);
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}
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void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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MachineInstr *begin,
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MachineInstr *end,
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unsigned NumRegionInstrs) const {
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if (needsAggressiveScheduling(DarwinDirective)) {
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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}
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// Spilling is generally expensive on all PPC cores, so always enable
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// register-pressure tracking.
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Policy.ShouldTrackPressure = true;
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}
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bool PPCSubtarget::useAA() const {
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// Use AA during code generation for the embedded cores.
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return needsAggressiveScheduling(DarwinDirective);
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}
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bool PPCSubtarget::enableSubRegLiveness() const {
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return UseSubRegLiveness;
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}
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bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
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bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
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