mirror of
https://github.com/c64scene-ar/llvm-6502.git
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86f9adb8be
This allows the (many) pseudo-instructions we have that map onto a single real instruction to have their expansion during MC lowering handled automatically instead of the current cumbersome manual expansion required. These sorts of pseudos are common when an instruction is used in situations that require different MachineInstr flags (isTerminator, isBranch, et. al.) than the generic instruction description has. For example, using a move to the PC to implement a branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134704 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
1.4 KiB
CMake
61 lines
1.4 KiB
CMake
set(LLVM_REQUIRES_EH 1)
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set(LLVM_REQUIRES_RTTI 1)
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set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR})
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add_llvm_utility(tblgen
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ARMDecoderEmitter.cpp
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AsmMatcherEmitter.cpp
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AsmWriterEmitter.cpp
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AsmWriterInst.cpp
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CallingConvEmitter.cpp
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ClangASTNodesEmitter.cpp
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ClangAttrEmitter.cpp
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ClangDiagnosticsEmitter.cpp
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ClangSACheckersEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenInstruction.cpp
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CodeGenRegisters.cpp
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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DAGISelMatcherOpt.cpp
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DAGISelMatcher.cpp
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DisassemblerEmitter.cpp
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EDEmitter.cpp
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Error.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
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InstrEnumEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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LLVMCConfigurationEmitter.cpp
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NeonEmitter.cpp
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OptParserEmitter.cpp
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PseudoLoweringEmitter.cpp
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Record.cpp
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RegisterInfoEmitter.cpp
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SetTheory.cpp
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StringMatcher.cpp
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SubtargetEmitter.cpp
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TGLexer.cpp
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TGParser.cpp
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TGValueTypes.cpp
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TableGen.cpp
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TableGenBackend.cpp
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X86DisassemblerTables.cpp
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X86RecognizableInstr.cpp
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)
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target_link_libraries(tblgen LLVMSupport)
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if( MINGW )
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target_link_libraries(tblgen imagehlp psapi)
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endif( MINGW )
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if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD AND NOT BEOS )
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target_link_libraries(tblgen pthread)
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endif()
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install(TARGETS tblgen RUNTIME DESTINATION bin)
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