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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239079 91177308-0d34-0410-b5e6-96231b3b80d8
206 lines
5.5 KiB
C++
206 lines
5.5 KiB
C++
//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MCInst and MCOperand classes, which
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// is the basic representation used to represent low-level machine code
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// instructions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCINST_H
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#define LLVM_MC_MCINST_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/SMLoc.h"
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namespace llvm {
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class raw_ostream;
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class MCAsmInfo;
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class MCInstPrinter;
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class MCExpr;
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class MCInst;
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/// \brief Instances of this class represent operands of the MCInst class.
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/// This is a simple discriminated union.
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class MCOperand {
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enum MachineOperandType : unsigned char {
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kInvalid, ///< Uninitialized.
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kRegister, ///< Register operand.
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kImmediate, ///< Immediate operand.
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kFPImmediate, ///< Floating-point immediate operand.
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kExpr, ///< Relocatable immediate operand.
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kInst ///< Sub-instruction operand.
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};
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MachineOperandType Kind;
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union {
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unsigned RegVal;
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int64_t ImmVal;
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double FPImmVal;
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const MCExpr *ExprVal;
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const MCInst *InstVal;
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};
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public:
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MCOperand() : Kind(kInvalid), FPImmVal(0.0) {}
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bool isValid() const { return Kind != kInvalid; }
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bool isReg() const { return Kind == kRegister; }
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bool isImm() const { return Kind == kImmediate; }
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bool isFPImm() const { return Kind == kFPImmediate; }
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bool isExpr() const { return Kind == kExpr; }
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bool isInst() const { return Kind == kInst; }
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/// \brief Returns the register number.
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unsigned getReg() const {
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assert(isReg() && "This is not a register operand!");
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return RegVal;
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}
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/// \brief Set the register number.
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void setReg(unsigned Reg) {
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assert(isReg() && "This is not a register operand!");
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RegVal = Reg;
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}
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int64_t getImm() const {
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assert(isImm() && "This is not an immediate");
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return ImmVal;
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}
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void setImm(int64_t Val) {
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assert(isImm() && "This is not an immediate");
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ImmVal = Val;
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}
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double getFPImm() const {
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assert(isFPImm() && "This is not an FP immediate");
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return FPImmVal;
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}
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void setFPImm(double Val) {
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assert(isFPImm() && "This is not an FP immediate");
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FPImmVal = Val;
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}
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const MCExpr *getExpr() const {
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assert(isExpr() && "This is not an expression");
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return ExprVal;
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}
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void setExpr(const MCExpr *Val) {
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assert(isExpr() && "This is not an expression");
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ExprVal = Val;
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}
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const MCInst *getInst() const {
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assert(isInst() && "This is not a sub-instruction");
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return InstVal;
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}
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void setInst(const MCInst *Val) {
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assert(isInst() && "This is not a sub-instruction");
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InstVal = Val;
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}
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static MCOperand createReg(unsigned Reg) {
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MCOperand Op;
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Op.Kind = kRegister;
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Op.RegVal = Reg;
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return Op;
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}
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static MCOperand createImm(int64_t Val) {
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MCOperand Op;
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Op.Kind = kImmediate;
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Op.ImmVal = Val;
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return Op;
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}
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static MCOperand createFPImm(double Val) {
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MCOperand Op;
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Op.Kind = kFPImmediate;
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Op.FPImmVal = Val;
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return Op;
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}
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static MCOperand createExpr(const MCExpr *Val) {
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MCOperand Op;
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Op.Kind = kExpr;
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Op.ExprVal = Val;
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return Op;
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}
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static MCOperand createInst(const MCInst *Val) {
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MCOperand Op;
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Op.Kind = kInst;
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Op.InstVal = Val;
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return Op;
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}
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void print(raw_ostream &OS) const;
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void dump() const;
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};
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template <> struct isPodLike<MCOperand> { static const bool value = true; };
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/// \brief Instances of this class represent a single low-level machine
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/// instruction.
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class MCInst {
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unsigned Opcode;
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SMLoc Loc;
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SmallVector<MCOperand, 8> Operands;
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public:
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MCInst() : Opcode(0) {}
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void setOpcode(unsigned Op) { Opcode = Op; }
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unsigned getOpcode() const { return Opcode; }
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void setLoc(SMLoc loc) { Loc = loc; }
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SMLoc getLoc() const { return Loc; }
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const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
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MCOperand &getOperand(unsigned i) { return Operands[i]; }
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unsigned getNumOperands() const { return Operands.size(); }
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void addOperand(const MCOperand &Op) { Operands.push_back(Op); }
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typedef SmallVectorImpl<MCOperand>::iterator iterator;
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typedef SmallVectorImpl<MCOperand>::const_iterator const_iterator;
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void clear() { Operands.clear(); }
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void erase(iterator I) { Operands.erase(I); }
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size_t size() const { return Operands.size(); }
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iterator begin() { return Operands.begin(); }
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const_iterator begin() const { return Operands.begin(); }
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iterator end() { return Operands.end(); }
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const_iterator end() const { return Operands.end(); }
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iterator insert(iterator I, const MCOperand &Op) {
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return Operands.insert(I, Op);
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}
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void print(raw_ostream &OS) const;
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void dump() const;
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/// \brief Dump the MCInst as prettily as possible using the additional MC
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/// structures, if given. Operators are separated by the \p Separator
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/// string.
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void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer = nullptr,
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StringRef Separator = " ") const;
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};
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inline raw_ostream& operator<<(raw_ostream &OS, const MCOperand &MO) {
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MO.print(OS);
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return OS;
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}
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inline raw_ostream& operator<<(raw_ostream &OS, const MCInst &MI) {
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MI.print(OS);
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return OS;
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}
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} // end namespace llvm
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#endif
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