mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
255 lines
9.4 KiB
LLVM
255 lines
9.4 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@f1 = common global float 0.000000e+00, align 4
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@f2 = common global float 0.000000e+00, align 4
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@b1 = common global i32 0, align 4
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@d1 = common global double 0.000000e+00, align 8
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@d2 = common global double 0.000000e+00, align 8
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; Function Attrs: nounwind
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define void @feq1() {
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entry:
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%0 = load float, float* @f1, align 4
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%1 = load float, float* @f2, align 4
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%cmp = fcmp oeq float %0, %1
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; CHECK-LABEL: feq1:
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; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
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; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
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; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]
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; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @fne1() {
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entry:
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%0 = load float, float* @f1, align 4
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%1 = load float, float* @f2, align 4
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%cmp = fcmp une float %0, %1
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; CHECK-LABEL: fne1:
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; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
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; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
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; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]
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; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @flt1() {
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entry:
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%0 = load float, float* @f1, align 4
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%1 = load float, float* @f2, align 4
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%cmp = fcmp olt float %0, %1
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; CHECK-LABEL: flt1:
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; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
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; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
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; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]]
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; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @fgt1() {
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entry:
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%0 = load float, float* @f1, align 4
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%1 = load float, float* @f2, align 4
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%cmp = fcmp ogt float %0, %1
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; CHECK-LABEL: fgt1:
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; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
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; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
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; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]]
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; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @fle1() {
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entry:
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%0 = load float, float* @f1, align 4
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%1 = load float, float* @f2, align 4
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%cmp = fcmp ole float %0, %1
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; CHECK-LABEL: fle1:
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; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
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; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
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; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]]
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; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @fge1() {
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entry:
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%0 = load float, float* @f1, align 4
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%1 = load float, float* @f2, align 4
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%cmp = fcmp oge float %0, %1
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; CHECK-LABEL: fge1:
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; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
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; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
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; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]]
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; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @deq1() {
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entry:
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%0 = load double, double* @d1, align 8
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%1 = load double, double* @d2, align 8
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%cmp = fcmp oeq double %0, %1
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; CHECK-LABEL: deq1:
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; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
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; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
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; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]
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; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @dne1() {
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entry:
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%0 = load double, double* @d1, align 8
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%1 = load double, double* @d2, align 8
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%cmp = fcmp une double %0, %1
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; CHECK-LABEL: dne1:
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; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
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; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
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; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]
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; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @dlt1() {
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entry:
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%0 = load double, double* @d1, align 8
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%1 = load double, double* @d2, align 8
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%cmp = fcmp olt double %0, %1
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; CHECK-LABEL: dlt1:
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; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
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; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
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; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]]
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; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @dgt1() {
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entry:
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%0 = load double, double* @d1, align 8
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%1 = load double, double* @d2, align 8
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%cmp = fcmp ogt double %0, %1
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; CHECK-LABEL: dgt1:
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; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
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; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
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; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]]
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; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @dle1() {
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entry:
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%0 = load double, double* @d1, align 8
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%1 = load double, double* @d2, align 8
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%cmp = fcmp ole double %0, %1
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; CHECK-LABEL: dle1:
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; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
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; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
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; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]]
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; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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; Function Attrs: nounwind
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define void @dge1() {
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entry:
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%0 = load double, double* @d1, align 8
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%1 = load double, double* @d2, align 8
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%cmp = fcmp oge double %0, %1
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; CHECK-LABEL: dge1:
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; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
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; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
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; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
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; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
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; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
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; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]]
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; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @b1, align 4
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ret void
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}
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