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Track new virtual registers by register number, rather than by the live interval created for them. This is the first step in separating the creation of new virtual registers and new live intervals. Eventually live intervals will be created and populated on demand after the virtual registers have been created and used in instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188434 91177308-0d34-0410-b5e6-96231b3b80d8
146 lines
5.4 KiB
C++
146 lines
5.4 KiB
C++
//===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RegAllocBase class which provides comon functionality
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// for LiveIntervalUnion-based register allocators.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RegAllocBase.h"
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#include "Spiller.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/LiveRegMatrix.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#ifndef NDEBUG
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#include "llvm/ADT/SparseBitVector.h"
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#endif
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Timer.h"
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using namespace llvm;
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STATISTIC(NumNewQueued , "Number of new live ranges queued");
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// Temporary verification option until we can put verification inside
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// MachineVerifier.
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static cl::opt<bool, true>
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VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
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cl::desc("Verify during register allocation"));
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const char RegAllocBase::TimerGroupName[] = "Register Allocation";
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bool RegAllocBase::VerifyEnabled = false;
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//===----------------------------------------------------------------------===//
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// RegAllocBase Implementation
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//===----------------------------------------------------------------------===//
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void RegAllocBase::init(VirtRegMap &vrm,
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LiveIntervals &lis,
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LiveRegMatrix &mat) {
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TRI = &vrm.getTargetRegInfo();
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MRI = &vrm.getRegInfo();
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VRM = &vrm;
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LIS = &lis;
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Matrix = &mat;
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MRI->freezeReservedRegs(vrm.getMachineFunction());
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RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
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}
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// Visit all the live registers. If they are already assigned to a physical
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// register, unify them with the corresponding LiveIntervalUnion, otherwise push
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// them on the priority queue for later assignment.
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void RegAllocBase::seedLiveRegs() {
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NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (MRI->reg_nodbg_empty(Reg))
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continue;
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enqueue(&LIS->getInterval(Reg));
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}
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}
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// Top-level driver to manage the queue of unassigned VirtRegs and call the
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// selectOrSplit implementation.
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void RegAllocBase::allocatePhysRegs() {
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seedLiveRegs();
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// Continue assigning vregs one at a time to available physical registers.
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while (LiveInterval *VirtReg = dequeue()) {
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assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
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// Unused registers can appear when the spiller coalesces snippets.
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if (MRI->reg_nodbg_empty(VirtReg->reg)) {
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DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
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LIS->removeInterval(VirtReg->reg);
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continue;
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}
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// Invalidate all interference queries, live ranges could have changed.
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Matrix->invalidateVirtRegs();
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// selectOrSplit requests the allocator to return an available physical
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// register if possible and populate a list of new live intervals that
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// result from splitting.
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DEBUG(dbgs() << "\nselectOrSplit "
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<< MRI->getRegClass(VirtReg->reg)->getName()
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<< ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
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typedef SmallVector<unsigned, 4> VirtRegVec;
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VirtRegVec SplitVRegs;
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unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
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if (AvailablePhysReg == ~0u) {
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// selectOrSplit failed to find a register!
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const char *Msg = "ran out of registers during register allocation";
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// Probably caused by an inline asm.
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MachineInstr *MI;
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for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
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(MI = I.skipInstruction());)
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if (MI->isInlineAsm())
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break;
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if (MI)
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MI->emitError(Msg);
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else
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report_fatal_error(Msg);
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// Keep going after reporting the error.
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VRM->assignVirt2Phys(VirtReg->reg,
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RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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continue;
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}
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if (AvailablePhysReg)
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Matrix->assign(*VirtReg, AvailablePhysReg);
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for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
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I != E; ++I) {
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LiveInterval *SplitVirtReg = &LIS->getInterval(*I);
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assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
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if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
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DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
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LIS->removeInterval(SplitVirtReg->reg);
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continue;
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}
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DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
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assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
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"expect split value in virtual register");
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enqueue(SplitVirtReg);
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++NumNewQueued;
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}
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}
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}
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