llvm-6502/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
Amaury de la Vieuville 9eefea009f ARM: fix VMOVvnf32 decoding when ambiguous with VCVT
Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:54:05 +00:00

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# VMOV cmode=0b1111 op=1
# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
# VMOV cmode=0b1111 op=1
# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding