mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 18:30:04 +00:00
46846844ee
This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226597 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
1.9 KiB
C++
67 lines
1.9 KiB
C++
//===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
#ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
|
|
#define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
|
|
|
|
#include "AMDGPUMachineFunction.h"
|
|
#include "SIRegisterInfo.h"
|
|
#include <map>
|
|
|
|
namespace llvm {
|
|
|
|
class MachineRegisterInfo;
|
|
|
|
/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
|
|
/// tells the hardware which interpolation parameters to load.
|
|
class SIMachineFunctionInfo : public AMDGPUMachineFunction {
|
|
void anchor() override;
|
|
|
|
unsigned TIDReg;
|
|
bool HasSpilledVGPRs;
|
|
|
|
public:
|
|
|
|
struct SpilledReg {
|
|
unsigned VGPR;
|
|
int Lane;
|
|
SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
|
|
SpilledReg() : VGPR(0), Lane(-1) { }
|
|
bool hasLane() { return Lane != -1;}
|
|
};
|
|
|
|
// SIMachineFunctionInfo definition
|
|
|
|
SIMachineFunctionInfo(const MachineFunction &MF);
|
|
SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
|
|
unsigned SubIdx);
|
|
unsigned PSInputAddr;
|
|
unsigned NumUserSGPRs;
|
|
std::map<unsigned, unsigned> LaneVGPRs;
|
|
unsigned LDSWaveSpillSize;
|
|
unsigned ScratchOffsetReg;
|
|
bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
|
|
unsigned getTIDReg() const { return TIDReg; };
|
|
void setTIDReg(unsigned Reg) { TIDReg = Reg; }
|
|
bool hasSpilledVGPRs() const { return HasSpilledVGPRs; }
|
|
void setHasSpilledVGPRs(bool Spill = true) { HasSpilledVGPRs = Spill; }
|
|
|
|
unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
|
|
#endif
|