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https://github.com/c64scene-ar/llvm-6502.git
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d24ba9ff6e
As Andy pointed out to me a long time ago, there are no structural hazards in the later pipeline stages of the A2, and so modeling them is useless. Also, modeling the top pre-dispatch stages is deceiving because, when multiple hardware threads are active, those resources are shared among the threads. The bypass definitions were mostly wrong, and so those have been removed. The resulting itinerary is much simpler, and more accurate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190562 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
6.6 KiB
TableGen
156 lines
6.6 KiB
TableGen
//===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Primary reference:
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// A2 Processor User's Manual.
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// IBM (as updated in) 2010.
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//===----------------------------------------------------------------------===//
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// Functional units on the PowerPC A2 chip sets
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//
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def XU : FuncUnit; // XU pipeline
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def FU : FuncUnit; // FI pipeline
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//
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// This file defines the itinerary class data for the PPC A2 processor.
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//
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//===----------------------------------------------------------------------===//
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def PPCA2Itineraries : ProcessorItineraries<
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[XU, FU], [], [
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InstrItinData<IntSimple , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<IntGeneral , [InstrStage<1, [XU]>],
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[2, 1, 1]>,
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InstrItinData<IntCompare , [InstrStage<1, [XU]>],
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[2, 1, 1]>,
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InstrItinData<IntDivW , [InstrStage<1, [XU]>],
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[39, 1, 1]>,
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InstrItinData<IntDivD , [InstrStage<1, [XU]>],
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[71, 1, 1]>,
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InstrItinData<IntMulHW , [InstrStage<1, [XU]>],
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[5, 1, 1]>,
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InstrItinData<IntMulHWU , [InstrStage<1, [XU]>],
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[5, 1, 1]>,
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InstrItinData<IntMulLI , [InstrStage<1, [XU]>],
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[6, 1, 1]>,
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InstrItinData<IntRotate , [InstrStage<1, [XU]>],
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[2, 1, 1]>,
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InstrItinData<IntRotateD , [InstrStage<1, [XU]>],
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[2, 1, 1]>,
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InstrItinData<IntRotateDI , [InstrStage<1, [XU]>],
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[2, 1, 1]>,
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InstrItinData<IntShift , [InstrStage<1, [XU]>],
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[2, 1, 1]>,
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InstrItinData<IntTrapW , [InstrStage<1, [XU]>],
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[2, 1]>,
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InstrItinData<IntTrapD , [InstrStage<1, [XU]>],
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[2, 1]>,
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InstrItinData<BrB , [InstrStage<1, [XU]>],
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[6, 1, 1]>,
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InstrItinData<BrCR , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<BrMCR , [InstrStage<1, [XU]>],
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[5, 1, 1]>,
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InstrItinData<BrMCRX , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<LdStDCBA , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<LdStDCBF , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<LdStDCBI , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<LdStLoad , [InstrStage<1, [XU]>],
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[6, 1, 1]>,
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InstrItinData<LdStLoadUpd , [InstrStage<1, [XU]>],
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[6, 2, 1, 1]>,
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InstrItinData<LdStLDU , [InstrStage<1, [XU]>],
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[6, 1, 1]>,
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InstrItinData<LdStStore , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<LdStStoreUpd, [InstrStage<1, [XU]>],
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[2, 1, 1, 1]>,
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InstrItinData<LdStICBI, [InstrStage<1, [XU]>],
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[16, 1, 1]>,
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InstrItinData<LdStSTFD , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<LdStSTFDU , [InstrStage<1, [XU]>],
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[2, 1, 1, 1]>,
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InstrItinData<LdStLFD , [InstrStage<1, [XU]>],
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[7, 1, 1]>,
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InstrItinData<LdStLFDU , [InstrStage<1, [XU]>],
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[7, 2, 1, 1]>,
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InstrItinData<LdStLHA , [InstrStage<1, [XU]>],
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[6, 1, 1]>,
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InstrItinData<LdStLHAU , [InstrStage<1, [XU]>],
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[6, 2, 1, 1]>,
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InstrItinData<LdStLWARX , [InstrStage<1, [XU]>],
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[82, 1, 1]>, // L2 latency
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InstrItinData<LdStSTD , [InstrStage<1, [XU]>],
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[1, 1, 1]>,
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InstrItinData<LdStSTDU , [InstrStage<1, [XU]>],
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[2, 1, 1, 1]>,
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InstrItinData<LdStSTDCX , [InstrStage<1, [XU]>],
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[82, 1, 1]>, // L2 latency
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InstrItinData<LdStSTWCX , [InstrStage<1, [XU]>],
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[82, 1, 1]>, // L2 latency
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InstrItinData<LdStSync , [InstrStage<1, [XU]>],
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[6]>,
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InstrItinData<SprISYNC , [InstrStage<1, [XU]>],
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[16]>,
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InstrItinData<SprMTMSR , [InstrStage<1, [XU]>],
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[16, 1]>,
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InstrItinData<SprMFCR , [InstrStage<1, [XU]>],
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[6, 1]>,
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InstrItinData<SprMFMSR , [InstrStage<1, [XU]>],
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[4, 1]>,
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InstrItinData<SprMFSPR , [InstrStage<1, [XU]>],
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[6, 1]>,
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InstrItinData<SprMFTB , [InstrStage<1, [XU]>],
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[4, 1]>,
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InstrItinData<SprMTSPR , [InstrStage<1, [XU]>],
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[6, 1]>,
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InstrItinData<SprRFI , [InstrStage<1, [XU]>],
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[16]>,
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InstrItinData<SprSC , [InstrStage<1, [XU]>],
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[16]>,
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InstrItinData<FPGeneral , [InstrStage<1, [FU]>],
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[6, 1, 1]>,
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InstrItinData<FPAddSub , [InstrStage<1, [FU]>],
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[6, 1, 1]>,
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InstrItinData<FPCompare , [InstrStage<1, [FU]>],
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[5, 1, 1]>,
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InstrItinData<FPDivD , [InstrStage<1, [FU]>],
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[72, 1, 1]>,
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InstrItinData<FPDivS , [InstrStage<1, [FU]>],
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[59, 1, 1]>,
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InstrItinData<FPSqrt , [InstrStage<1, [FU]>],
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[69, 1, 1]>,
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InstrItinData<FPFused , [InstrStage<1, [FU]>],
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[6, 1, 1, 1]>,
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InstrItinData<FPRes , [InstrStage<1, [FU]>],
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[6, 1]>
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]>;
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// ===---------------------------------------------------------------------===//
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// A2 machine model for scheduling and other instruction cost heuristics.
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def PPCA2Model : SchedMachineModel {
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let IssueWidth = 1; // 2 micro-ops are dispatched per cycle.
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let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 6; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 13;
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let Itineraries = PPCA2Itineraries;
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}
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