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https://github.com/c64scene-ar/llvm-6502.git
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ca795b61be
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
8.5 KiB
LLVM
218 lines
8.5 KiB
LLVM
; Test the MSA floating point to integer intrinsics that are encoded with the
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; 2RF instruction format. This includes conversions but other instructions such
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; as fclass are also here.
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_fclass_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_fclass_w_ARG1
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%1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0)
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store <4 x i32> %1, <4 x i32>* @llvm_mips_fclass_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind
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; CHECK: llvm_mips_fclass_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_w_ARG1)
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; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: fclass.w [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_w_RES)
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; CHECK-DAG: st.w [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_fclass_w_test
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;
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@llvm_mips_fclass_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_fclass_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_fclass_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_fclass_d_ARG1
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%1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0)
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store <2 x i64> %1, <2 x i64>* @llvm_mips_fclass_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind
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; CHECK: llvm_mips_fclass_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_d_ARG1)
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; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: fclass.d [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_d_RES)
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; CHECK-DAG: st.d [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_fclass_d_test
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;
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@llvm_mips_ftrunc_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_ftrunc_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_ftrunc_s_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_ftrunc_s_w_ARG1
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%1 = tail call <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float> %0)
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store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_s_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind
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; CHECK: llvm_mips_ftrunc_s_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_ARG1)
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; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftrunc_s.w [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_RES)
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; CHECK-DAG: st.w [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftrunc_s_w_test
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;
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@llvm_mips_ftrunc_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_ftrunc_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_ftrunc_s_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_ftrunc_s_d_ARG1
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%1 = tail call <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double> %0)
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store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_s_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind
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; CHECK: llvm_mips_ftrunc_s_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_ARG1)
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; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftrunc_s.d [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_RES)
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; CHECK-DAG: st.d [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftrunc_s_d_test
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;
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@llvm_mips_ftrunc_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_ftrunc_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_ftrunc_u_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_ftrunc_u_w_ARG1
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%1 = tail call <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float> %0)
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store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_u_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float>) nounwind
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; CHECK: llvm_mips_ftrunc_u_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_ARG1)
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; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftrunc_u.w [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_RES)
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; CHECK-DAG: st.w [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftrunc_u_w_test
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;
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@llvm_mips_ftrunc_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_ftrunc_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_ftrunc_u_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_ftrunc_u_d_ARG1
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%1 = tail call <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double> %0)
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store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_u_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double>) nounwind
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; CHECK: llvm_mips_ftrunc_u_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_ARG1)
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; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftrunc_u.d [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_RES)
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; CHECK-DAG: st.d [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftrunc_u_d_test
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;
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@llvm_mips_ftint_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_ftint_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_ftint_s_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_ftint_s_w_ARG1
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%1 = tail call <4 x i32> @llvm.mips.ftint.s.w(<4 x float> %0)
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store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_s_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.ftint.s.w(<4 x float>) nounwind
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; CHECK: llvm_mips_ftint_s_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_w_ARG1)
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; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftint_s.w [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_w_RES)
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; CHECK-DAG: st.w [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftint_s_w_test
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;
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@llvm_mips_ftint_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_ftint_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_ftint_s_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_ftint_s_d_ARG1
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%1 = tail call <2 x i64> @llvm.mips.ftint.s.d(<2 x double> %0)
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store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_s_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.ftint.s.d(<2 x double>) nounwind
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; CHECK: llvm_mips_ftint_s_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_d_ARG1)
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; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftint_s.d [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_d_RES)
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; CHECK-DAG: st.d [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftint_s_d_test
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;
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@llvm_mips_ftint_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
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@llvm_mips_ftint_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_ftint_u_w_test() nounwind {
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entry:
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%0 = load <4 x float>* @llvm_mips_ftint_u_w_ARG1
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%1 = tail call <4 x i32> @llvm.mips.ftint.u.w(<4 x float> %0)
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store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_u_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.ftint.u.w(<4 x float>) nounwind
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; CHECK: llvm_mips_ftint_u_w_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_w_ARG1)
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; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftint_u.w [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_w_RES)
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; CHECK-DAG: st.w [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftint_u_w_test
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;
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@llvm_mips_ftint_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
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@llvm_mips_ftint_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_ftint_u_d_test() nounwind {
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entry:
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%0 = load <2 x double>* @llvm_mips_ftint_u_d_ARG1
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%1 = tail call <2 x i64> @llvm.mips.ftint.u.d(<2 x double> %0)
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store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_u_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.ftint.u.d(<2 x double>) nounwind
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; CHECK: llvm_mips_ftint_u_d_test:
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_d_ARG1)
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; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ftint_u.d [[WD:\$w[0-9]+]], [[WS]]
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_d_RES)
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; CHECK-DAG: st.d [[WD]], 0([[R2]])
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; CHECK: .size llvm_mips_ftint_u_d_test
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;
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