mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
9e0f77e34e
This reverts commit r197466. The MachineCSE fix that required the -mcpu flag has been disabled until more work can be done to fix downstream issues. Adding -mcpu wasn't the right workaround anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197624 91177308-0d34-0410-b5e6-96231b3b80d8
269 lines
7.0 KiB
LLVM
269 lines
7.0 KiB
LLVM
; Test high-part i64->i128 multiplications.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Check zero-extended multiplication in which only the high part is used.
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define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: mlgr %r2, %r4
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; CHECK: br %r14
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check sign-extended multiplication in which only the high part is used.
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; This needs a rather convoluted sequence.
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define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK-DAG: srag [[RES1:%r[0-5]]], %r3, 63
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; CHECK-DAG: srag [[RES2:%r[0-5]]], %r4, 63
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; CHECK-DAG: ngr [[RES1]], %r4
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; CHECK-DAG: ngr [[RES2]], %r3
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; CHECK-DAG: agr [[RES2]], [[RES1]]
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; CHECK-DAG: mlgr %r2, %r4
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; CHECK: sgr %r2, [[RES2]]
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; CHECK: br %r14
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%ax = sext i64 %a to i128
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%bx = sext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check zero-extended multiplication in which only part of the high half
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; is used.
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define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: mlgr %r2, %r4
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; CHECK: srlg %r2, %r2, 3
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; CHECK: br %r14
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 67
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check zero-extended multiplication in which the result is split into
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; high and low halves.
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define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: mlgr %r2, %r4
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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%low = trunc i128 %mulx to i64
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%or = or i64 %high, %low
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ret i64 %or
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}
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; Check division by a constant, which should use multiplication instead.
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define i64 @f5(i64 %dummy, i64 %a) {
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; CHECK-LABEL: f5:
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; CHECK: mlgr %r2,
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; CHECK: srlg %r2, %r2,
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; CHECK: br %r14
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%res = udiv i64 %a, 1234
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ret i64 %res
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}
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; Check MLG with no displacement.
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define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: mlg %r2, 0(%r4)
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; CHECK: br %r14
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%b = load i64 *%src
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check the high end of the aligned MLG range.
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define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: mlg %r2, 524280(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65535
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%b = load i64 *%ptr
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check the next doubleword up, which requires separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r4, 524288
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; CHECK: mlg %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65536
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%b = load i64 *%ptr
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check the high end of the negative aligned MLG range.
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define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: mlg %r2, -8(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -1
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%b = load i64 *%ptr
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check the low end of the MLG range.
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define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: mlg %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65536
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%b = load i64 *%ptr
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: agfi %r4, -524296
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; CHECK: mlg %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65537
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%b = load i64 *%ptr
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check that MLG allows an index.
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define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f12:
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; CHECK: mlg %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%b = load i64 *%ptr
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%ax = zext i64 %a to i128
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%bx = zext i64 %b to i128
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%mulx = mul i128 %ax, %bx
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%highx = lshr i128 %mulx, 64
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%high = trunc i128 %highx to i64
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ret i64 %high
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}
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; Check that multiplications of spilled values can use MLG rather than MLGR.
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define i64 @f13(i64 *%ptr0) {
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; CHECK-LABEL: f13:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: mlg {{%r[0-9]+}}, 160(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i64 *%ptr0, i64 2
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%ptr2 = getelementptr i64 *%ptr0, i64 4
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%ptr3 = getelementptr i64 *%ptr0, i64 6
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%ptr4 = getelementptr i64 *%ptr0, i64 8
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%ptr5 = getelementptr i64 *%ptr0, i64 10
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%ptr6 = getelementptr i64 *%ptr0, i64 12
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%ptr7 = getelementptr i64 *%ptr0, i64 14
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%ptr8 = getelementptr i64 *%ptr0, i64 16
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%ptr9 = getelementptr i64 *%ptr0, i64 18
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%val0 = load i64 *%ptr0
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%val1 = load i64 *%ptr1
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%val2 = load i64 *%ptr2
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%val3 = load i64 *%ptr3
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%val4 = load i64 *%ptr4
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%val5 = load i64 *%ptr5
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%val6 = load i64 *%ptr6
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%val7 = load i64 *%ptr7
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%val8 = load i64 *%ptr8
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%val9 = load i64 *%ptr9
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%ret = call i64 @foo()
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%retx = zext i64 %ret to i128
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%val0x = zext i64 %val0 to i128
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%mul0d = mul i128 %retx, %val0x
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%mul0x = lshr i128 %mul0d, 64
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%val1x = zext i64 %val1 to i128
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%mul1d = mul i128 %mul0x, %val1x
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%mul1x = lshr i128 %mul1d, 64
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%val2x = zext i64 %val2 to i128
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%mul2d = mul i128 %mul1x, %val2x
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%mul2x = lshr i128 %mul2d, 64
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%val3x = zext i64 %val3 to i128
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%mul3d = mul i128 %mul2x, %val3x
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%mul3x = lshr i128 %mul3d, 64
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%val4x = zext i64 %val4 to i128
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%mul4d = mul i128 %mul3x, %val4x
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%mul4x = lshr i128 %mul4d, 64
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%val5x = zext i64 %val5 to i128
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%mul5d = mul i128 %mul4x, %val5x
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%mul5x = lshr i128 %mul5d, 64
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%val6x = zext i64 %val6 to i128
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%mul6d = mul i128 %mul5x, %val6x
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%mul6x = lshr i128 %mul6d, 64
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%val7x = zext i64 %val7 to i128
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%mul7d = mul i128 %mul6x, %val7x
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%mul7x = lshr i128 %mul7d, 64
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%val8x = zext i64 %val8 to i128
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%mul8d = mul i128 %mul7x, %val8x
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%mul8x = lshr i128 %mul8d, 64
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%val9x = zext i64 %val9 to i128
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%mul9d = mul i128 %mul8x, %val9x
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%mul9x = lshr i128 %mul9d, 64
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%mul9 = trunc i128 %mul9x to i64
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ret i64 %mul9
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}
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