mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
e9915738be
FoldConstantArithmetic() only knows how to deal with a few target independent ISD opcodes. Bail early if it sees a target-specific ISD node. These node do funny things with operand types which may break the assumptions of the code that follows, and there's no actual folding that can be done anyway. For example, non-constant 256 bit vector shifts on X86 have a shift-amount operand that's a 128-bit v4i32 vector regardless of what the first operand type is and that breaks the assumption that the operand types must match. rdar://16530923 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205937 91177308-0d34-0410-b5e6-96231b3b80d8
269 lines
7.0 KiB
LLVM
269 lines
7.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; AVX2 Logical Shift Left
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define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
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entry:
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%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_1:
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; CHECK-NOT: vpsllw $0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
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entry:
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%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_2:
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; CHECK: vpaddw %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
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entry:
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%shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_3:
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; CHECK: vpsllw $15, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
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entry:
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%shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_slld_1:
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; CHECK-NOT: vpslld $0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
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entry:
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%shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_slld_2:
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; CHECK: vpaddd %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_vpslld_var(i32 %shift) {
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%amt = insertelement <8 x i32> undef, i32 %shift, i32 0
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%tmp = shl <8 x i32> <i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, i32 199>, %amt
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ret <8 x i32> %tmp
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}
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; CHECK-LABEL: test_vpslld_var:
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; CHECK: vpslld %xmm0, %ymm1, %ymm0
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; CHECK: ret
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define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
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entry:
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%shl = shl <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_slld_3:
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; CHECK: vpslld $31, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
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entry:
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%shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_1:
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; CHECK-NOT: vpsllq $0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
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entry:
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%shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_2:
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; CHECK: vpaddq %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
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entry:
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%shl = shl <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_3:
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; CHECK: vpsllq $63, %ymm0, %ymm0
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; CHECK: ret
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; AVX2 Arithmetic Shift
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define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
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entry:
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%shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_1:
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; CHECK-NOT: vpsraw $0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
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entry:
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%shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_2:
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; CHECK: vpsraw $1, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
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entry:
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%shl = ashr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_3:
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; CHECK: vpsraw $15, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
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entry:
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%shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srad_1:
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; CHECK-NOT: vpsrad $0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
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entry:
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%shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srad_2:
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; CHECK: vpsrad $1, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
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entry:
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%shl = ashr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srad_3:
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; CHECK: vpsrad $31, %ymm0, %ymm0
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; CHECK: ret
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; SSE Logical Shift Right
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define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
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entry:
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%shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_1:
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; CHECK-NOT: vpsrlw $0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
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entry:
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%shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_2:
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; CHECK: vpsrlw $1, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
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entry:
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%shl = lshr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_3:
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; CHECK: vpsrlw $15, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
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entry:
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%shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srld_1:
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; CHECK-NOT: vpsrld $0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
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entry:
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%shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srld_2:
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; CHECK: vpsrld $1, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
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entry:
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%shl = lshr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srld_3:
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; CHECK: vpsrld $31, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
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entry:
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%shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_1:
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; CHECK-NOT: vpsrlq $0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
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entry:
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%shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_2:
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; CHECK: vpsrlq $1, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
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entry:
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%shl = lshr <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_3:
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; CHECK: vpsrlq $63, %ymm0, %ymm0
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; CHECK: ret
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; CHECK-LABEL: @srl_trunc_and_v4i64
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; CHECK: vpand
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; CHECK-NEXT: vpsrlvd
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; CHECK: ret
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define <4 x i32> @srl_trunc_and_v4i64(<4 x i32> %x, <4 x i64> %y) nounwind {
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%and = and <4 x i64> %y, <i64 8, i64 8, i64 8, i64 8>
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%trunc = trunc <4 x i64> %and to <4 x i32>
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%sra = lshr <4 x i32> %x, %trunc
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ret <4 x i32> %sra
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}
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