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https://github.com/c64scene-ar/llvm-6502.git
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55d7d83b6c
This just adds the basics necessary for allocating the upper words to virtual registers (move, load and store). The move support is parameterised in a way that makes it easy to handle zero extensions, but the associated zero-extend patterns are added by a later patch. The easiest way of testing this seemed to be add a new "h" register constraint for high words. I don't expect the constraint to be useful in real inline asms, but it should work, so I didn't try to hide it behind an option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.9 KiB
LLVM
53 lines
1.9 KiB
LLVM
; Test high-word operations, using "h" constraints to force a high
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; register and "r" constraints to force a low register.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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; Test loads and stores involving mixtures of high and low registers.
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define void @f1(i32 *%ptr1, i32 *%ptr2) {
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; CHECK-LABEL: f1:
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; CHECK-DAG: lfh [[REG1:%r[0-5]]], 0(%r2)
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; CHECK-DAG: l [[REG2:%r[0-5]]], 0(%r3)
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; CHECK-DAG: lfh [[REG3:%r[0-5]]], 4096(%r2)
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; CHECK-DAG: ly [[REG4:%r[0-5]]], 524284(%r3)
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; CHECK: blah [[REG1]], [[REG2]], [[REG3]], [[REG4]]
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; CHECK-DAG: stfh [[REG1]], 0(%r2)
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; CHECK-DAG: st [[REG2]], 0(%r3)
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; CHECK-DAG: stfh [[REG3]], 4096(%r2)
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; CHECK-DAG: sty [[REG4]], 524284(%r3)
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; CHECK: br %r14
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%ptr3 = getelementptr i32 *%ptr1, i64 1024
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%ptr4 = getelementptr i32 *%ptr2, i64 131071
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%old1 = load i32 *%ptr1
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%old2 = load i32 *%ptr2
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%old3 = load i32 *%ptr3
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%old4 = load i32 *%ptr4
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%res = call { i32, i32, i32, i32 } asm "blah $0, $1, $2, $3",
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"=h,=r,=h,=r,0,1,2,3"(i32 %old1, i32 %old2, i32 %old3, i32 %old4)
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%new1 = extractvalue { i32, i32, i32, i32 } %res, 0
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%new2 = extractvalue { i32, i32, i32, i32 } %res, 1
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%new3 = extractvalue { i32, i32, i32, i32 } %res, 2
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%new4 = extractvalue { i32, i32, i32, i32 } %res, 3
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store i32 %new1, i32 *%ptr1
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store i32 %new2, i32 *%ptr2
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store i32 %new3, i32 *%ptr3
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store i32 %new4, i32 *%ptr4
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ret void
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}
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; Test moves involving mixtures of high and low registers.
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define i32 @f2(i32 %old) {
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; CHECK-LABEL: f2:
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; CHECK-DAG: risbhg [[REG1:%r[0-5]]], %r2, 0, 159, 32
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; CHECK-DAG: lr %r3, %r2
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; CHECK: stepa [[REG1]], %r2, %r3
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; CHECK: risbhg {{%r[0-5]}}, [[REG1]], 0, 159, 0
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; CHECK: stepb [[REG2:%r[0-5]]]
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; CHECK: risblg %r2, [[REG2]], 0, 159, 32
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; CHECK: br %r14
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%tmp = call i32 asm "stepa $1, $2, $3",
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"=h,0,{r2},{r3}"(i32 %old, i32 %old, i32 %old)
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%new = call i32 asm "stepb $1, $2", "=&h,0,h"(i32 %tmp, i32 %tmp)
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ret i32 %new
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}
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