Ulrich Weigand 5606fcae50 [PowerPC] Add asm parser support for CR expressions ... This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-04 14:24:00 +00:00
..
Analysis	Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.	2013-07-04 01:31:24 +00:00
AsmParser
Bitcode
CodeGen	Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.	2013-07-04 13:54:20 +00:00
DebugInfo
ExecutionEngine	Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.	2013-07-04 01:31:24 +00:00
IR	Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.	2013-07-04 01:31:24 +00:00
IRReader
Linker
MC	[PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD	2013-07-02 21:29:06 +00:00
Object	Add support for gnu archives with a string table and no symtab.	2013-07-03 15:57:14 +00:00
Option
Support	Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.	2013-07-04 01:31:24 +00:00
TableGen
Target	[PowerPC] Add asm parser support for CR expressions	2013-07-04 14:24:00 +00:00
Transforms	SimplifyCFG: Teach switch generation some patterns that instcombine forms.	2013-07-04 14:22:02 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile