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https://github.com/c64scene-ar/llvm-6502.git
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974a445bd9
subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
340 lines
10 KiB
C++
340 lines
10 KiB
C++
//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARM specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMSubtarget.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOptions.h"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "ARMGenSubtargetInfo.inc"
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using namespace llvm;
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static cl::opt<bool>
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ReserveR9("arm-reserve-r9", cl::Hidden,
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cl::desc("Reserve R9, making it unavailable as GPR"));
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static cl::opt<bool>
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ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
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static cl::opt<bool>
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UseFusedMulOps("arm-use-mulops",
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cl::init(true), cl::Hidden);
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enum AlignMode {
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DefaultAlign,
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StrictAlign,
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NoStrictAlign
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};
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static cl::opt<AlignMode>
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Align(cl::desc("Load/store alignment support"),
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cl::Hidden, cl::init(DefaultAlign),
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cl::values(
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clEnumValN(DefaultAlign, "arm-default-align",
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"Generate unaligned accesses only on hardware/OS "
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"combinations that are known to support them"),
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clEnumValN(StrictAlign, "arm-strict-align",
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"Disallow all unaligned memory accesses"),
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clEnumValN(NoStrictAlign, "arm-no-strict-align",
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"Allow unaligned memory accesses"),
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clEnumValEnd));
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enum ITMode {
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DefaultIT,
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RestrictedIT,
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NoRestrictedIT
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};
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static cl::opt<ITMode>
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IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
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cl::ZeroOrMore,
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cl::values(clEnumValN(DefaultIT, "arm-default-it",
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"Generate IT block based on arch"),
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clEnumValN(RestrictedIT, "arm-restrict-it",
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"Disallow deprecated IT based on ARMv8"),
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clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
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"Allow IT blocks based on ARMv7"),
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clEnumValEnd));
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ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, const TargetOptions &Options)
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: ARMGenSubtargetInfo(TT, CPU, FS)
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, ARMProcFamily(Others)
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, ARMProcClass(None)
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, stackAlignment(4)
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, CPUString(CPU)
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, TargetTriple(TT)
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, Options(Options)
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, TargetABI(ARM_ABI_UNKNOWN) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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}
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void ARMSubtarget::initializeEnvironment() {
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HasV4TOps = false;
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HasV5TOps = false;
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HasV5TEOps = false;
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HasV6Ops = false;
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HasV6MOps = false;
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HasV6T2Ops = false;
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HasV7Ops = false;
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HasV8Ops = false;
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HasVFPv2 = false;
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HasVFPv3 = false;
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HasVFPv4 = false;
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HasFPARMv8 = false;
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HasNEON = false;
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MinSize = false;
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UseNEONForSinglePrecisionFP = false;
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UseMulOps = UseFusedMulOps;
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SlowFPVMLx = false;
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HasVMLxForwarding = false;
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SlowFPBrcc = false;
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InThumbMode = false;
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HasThumb2 = false;
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NoARM = false;
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PostRAScheduler = false;
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IsR9Reserved = ReserveR9;
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UseMovt = false;
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SupportsTailCall = false;
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HasFP16 = false;
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HasD16 = false;
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HasHardwareDivide = false;
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HasHardwareDivideInARM = false;
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HasT2ExtractPack = false;
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HasDataBarrier = false;
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Pref32BitThumb = false;
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AvoidCPSRPartialUpdate = false;
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AvoidMOVsShifterOperand = false;
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HasRAS = false;
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HasMPExtension = false;
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HasVirtualization = false;
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FPOnlySP = false;
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HasPerfMon = false;
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HasTrustZone = false;
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HasCrypto = false;
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HasCRC = false;
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AllowsUnalignedMem = false;
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Thumb2DSP = false;
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UseNaClTrap = false;
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UnsafeFPMath = false;
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}
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void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
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AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-cpu");
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Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-features");
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std::string CPU =
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!CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
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std::string FS =
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!FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
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if (!FS.empty()) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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}
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MinSize =
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FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
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}
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void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
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if (CPUString.empty()) {
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if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
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// Default to the Swift CPU when targeting armv7s/thumbv7s.
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CPUString = "swift";
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else
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CPUString = "generic";
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}
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// Insert the architecture feature derived from the target triple into the
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// feature string. This is important for setting features that are implied
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// based on the architecture version.
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std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
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CPUString);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS.str();
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else
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ArchFS = FS;
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}
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ParseSubtargetFeatures(CPUString, ArchFS);
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// FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
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// Assert this for now to make the change obvious.
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assert(hasV6T2Ops() || !hasThumb2());
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// Keep a pointer to static instruction cost data for the specified CPU.
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SchedModel = getSchedModelForCPU(CPUString);
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUString);
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if (TargetABI == ARM_ABI_UNKNOWN) {
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switch (TargetTriple.getEnvironment()) {
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case Triple::Android:
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case Triple::EABI:
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case Triple::EABIHF:
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case Triple::GNUEABI:
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case Triple::GNUEABIHF:
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case Triple::MachO:
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TargetABI = ARM_ABI_AAPCS;
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break;
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default:
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if (isTargetIOS() && isMClass())
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TargetABI = ARM_ABI_AAPCS;
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else
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TargetABI = ARM_ABI_APCS;
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break;
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}
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}
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if (isAAPCS_ABI())
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stackAlignment = 8;
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UseMovt = hasV6T2Ops() && ArmUseMOVT;
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if (isTargetMachO()) {
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IsR9Reserved = ReserveR9 | !HasV6Ops;
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SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
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} else
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IsR9Reserved = ReserveR9;
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if (!isThumb() || hasThumb2())
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PostRAScheduler = true;
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switch (Align) {
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case DefaultAlign:
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// Assume pre-ARMv6 doesn't support unaligned accesses.
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//
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// ARMv6 may or may not support unaligned accesses depending on the
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// SCTLR.U bit, which is architecture-specific. We assume ARMv6
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// Darwin targets support unaligned accesses, and others don't.
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//
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// ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
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// which raises an alignment fault on unaligned accesses. Linux
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// defaults this bit to 0 and handles it as a system-wide (not
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// per-process) setting. It is therefore safe to assume that ARMv7+
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// Linux targets support unaligned accesses. The same goes for NaCl.
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//
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// The above behavior is consistent with GCC.
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AllowsUnalignedMem = (
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(hasV7Ops() && (isTargetLinux() || isTargetNaCl())) ||
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(hasV6Ops() && isTargetMachO()));
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break;
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case StrictAlign:
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AllowsUnalignedMem = false;
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break;
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case NoStrictAlign:
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AllowsUnalignedMem = true;
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break;
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}
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switch (IT) {
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case DefaultIT:
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RestrictIT = hasV8Ops() ? true : false;
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break;
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case RestrictedIT:
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RestrictIT = true;
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break;
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case NoRestrictedIT:
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RestrictIT = false;
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break;
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}
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// NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
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uint64_t Bits = getFeatureBits();
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if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
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(Options.UnsafeFPMath || isTargetDarwin()))
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UseNEONForSinglePrecisionFP = true;
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}
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/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
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bool
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ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
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Reloc::Model RelocM) const {
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if (RelocM == Reloc::Static)
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return false;
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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bool isDecl = GV->hasAvailableExternallyLinkage();
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if (GV->isDeclaration() && !GV->isMaterializable())
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isDecl = true;
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if (!isTargetMachO()) {
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return false;
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return true;
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} else {
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if (RelocM == Reloc::PIC_) {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage())
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// Hidden $non_lazy_ptr reference.
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return true;
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return false;
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} else {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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}
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}
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return false;
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}
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unsigned ARMSubtarget::getMispredictionPenalty() const {
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return SchedModel->MispredictPenalty;
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}
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bool ARMSubtarget::hasSinCos() const {
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return getTargetTriple().getOS() == Triple::IOS &&
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!getTargetTriple().isOSVersionLT(7, 0);
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}
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bool ARMSubtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtargetInfo::ANTIDEP_NONE;
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return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
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}
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