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Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
216 lines
7.1 KiB
C++
216 lines
7.1 KiB
C++
//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate information gleaned from the
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// target register and register class definitions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_REGISTERS_H
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#define CODEGEN_REGISTERS_H
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#include "Record.h"
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#include "SetTheory.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SetVector.h"
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#include <cstdlib>
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#include <map>
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#include <string>
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#include <set>
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#include <vector>
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namespace llvm {
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class CodeGenRegBank;
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/// CodeGenRegister - Represents a register definition.
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struct CodeGenRegister {
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Record *TheDef;
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unsigned EnumValue;
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unsigned CostPerUse;
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// Map SubRegIndex -> Register.
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typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
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CodeGenRegister(Record *R, unsigned Enum);
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const std::string &getName() const;
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// Get a map of sub-registers computed lazily.
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// This includes unique entries for all sub-sub-registers.
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const SubRegMap &getSubRegs(CodeGenRegBank&);
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const SubRegMap &getSubRegs() const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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return SubRegs;
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}
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// Add sub-registers to OSet following a pre-order defined by the .td file.
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void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const;
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// List of super-registers in topological order, small to large.
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typedef std::vector<CodeGenRegister*> SuperRegList;
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// Get the list of super-registers.
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// This is only valid after computeDerivedInfo has visited all registers.
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const SuperRegList &getSuperRegs() const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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return SuperRegs;
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}
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// Order CodeGenRegister pointers by EnumValue.
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struct Less {
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bool operator()(const CodeGenRegister *A,
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const CodeGenRegister *B) const {
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return A->EnumValue < B->EnumValue;
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}
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};
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// Canonically ordered set.
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typedef std::set<const CodeGenRegister*, Less> Set;
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private:
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bool SubRegsComplete;
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SubRegMap SubRegs;
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SuperRegList SuperRegs;
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};
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class CodeGenRegisterClass {
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CodeGenRegister::Set Members;
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const std::vector<Record*> *Elements;
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std::vector<SmallVector<Record*, 16> > AltOrders;
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public:
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Record *TheDef;
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std::string Namespace;
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std::vector<MVT::SimpleValueType> VTs;
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unsigned SpillSize;
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unsigned SpillAlignment;
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int CopyCost;
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bool Allocatable;
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// Map SubRegIndex -> RegisterClass
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DenseMap<Record*,Record*> SubRegClasses;
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std::string AltOrderSelect;
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const std::string &getName() const;
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const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
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unsigned getNumValueTypes() const { return VTs.size(); }
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MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
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if (VTNum < VTs.size())
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return VTs[VTNum];
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assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
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abort();
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}
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// Return true if this this class contains the register.
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bool contains(const CodeGenRegister*) const;
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// Returns true if RC is a subclass.
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// RC is a sub-class of this class if it is a valid replacement for any
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// instruction operand where a register of this classis required. It must
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// satisfy these conditions:
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//
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// 1. All RC registers are also in this.
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// 2. The RC spill size must not be smaller than our spill size.
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// 3. RC spill alignment must be compatible with ours.
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//
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bool hasSubClass(const CodeGenRegisterClass *RC) const;
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// Returns an ordered list of class members.
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// The order of registers is the same as in the .td file.
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// No = 0 is the default allocation order, No = 1 is the first alternative.
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ArrayRef<Record*> getOrder(unsigned No = 0) const {
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if (No == 0)
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return *Elements;
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else
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return AltOrders[No - 1];
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}
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// Return the total number of allocation orders available.
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unsigned getNumOrders() const { return 1 + AltOrders.size(); }
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CodeGenRegisterClass(CodeGenRegBank&, Record *R);
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};
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// CodeGenRegBank - Represent a target's registers and the relations between
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// them.
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class CodeGenRegBank {
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RecordKeeper &Records;
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SetTheory Sets;
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std::vector<Record*> SubRegIndices;
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unsigned NumNamedIndices;
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std::vector<CodeGenRegister*> Registers;
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DenseMap<Record*, CodeGenRegister*> Def2Reg;
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std::vector<CodeGenRegisterClass> RegClasses;
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DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
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// Composite SubRegIndex instances.
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// Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
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typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
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CompositeMap Composite;
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// Populate the Composite map from sub-register relationships.
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void computeComposites();
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public:
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CodeGenRegBank(RecordKeeper&);
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SetTheory &getSets() { return Sets; }
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// Sub-register indices. The first NumNamedIndices are defined by the user
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// in the .td files. The rest are synthesized such that all sub-registers
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// have a unique name.
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const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
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unsigned getNumNamedIndices() { return NumNamedIndices; }
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// Map a SubRegIndex Record to its enum value.
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unsigned getSubRegIndexNo(Record *idx);
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// Find or create a sub-register index representing the A+B composition.
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Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
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const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
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// Find a register from its Record def.
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CodeGenRegister *getReg(Record*);
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const std::vector<CodeGenRegisterClass> &getRegClasses() {
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return RegClasses;
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}
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// Find a register class from its def.
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CodeGenRegisterClass *getRegClass(Record*);
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/// getRegisterClassForRegister - Find the register class that contains the
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/// specified physical register. If the register is not in a register
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/// class, return null. If the register is in multiple classes, and the
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/// classes have a superset-subset relationship and the same set of types,
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/// return the superclass. Otherwise return null.
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const CodeGenRegisterClass* getRegClassForRegister(Record *R);
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// Computed derived records such as missing sub-register indices.
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void computeDerivedInfo();
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// Compute full overlap sets for every register. These sets include the
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// rarely used aliases that are neither sub nor super-registers.
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//
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// Map[R1].count(R2) is reflexive and symmetric, but not transitive.
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//
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// If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
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void computeOverlaps(std::map<const CodeGenRegister*,
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CodeGenRegister::Set> &Map);
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};
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}
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#endif
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