Craig Topper 566f233ba6 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-15 20:46:47 +00:00
..
dg.exp
enhanced.txt	Insert dummy ED table entries for pseudo-instructions.	2011-10-10 18:30:16 +00:00
intel-syntax.txt	Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.	2011-10-02 21:08:12 +00:00
invalid-VEX-vvvv.txt	Add test case for PR10851.	2011-09-14 04:36:54 +00:00
simple-tests.txt	Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.	2011-10-15 20:46:47 +00:00
truncated-input.txt
x86-32.txt	Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.	2011-10-15 20:46:47 +00:00