mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c4d4b76efb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@847 91177308-0d34-0410-b5e6-96231b3b80d8
372 lines
11 KiB
C++
372 lines
11 KiB
C++
#include "llvm/CodeGen/LiveRangeInfo.h"
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LiveRangeInfo::LiveRangeInfo(const Method *const M,
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const TargetMachine& tm,
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vector<RegClass *> &RCL)
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: Meth(M), LiveRangeMap(),
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TM(tm), RegClassList(RCL),
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MRI( tm.getRegInfo()),
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CallRetInstrList()
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{ }
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// union two live ranges into one. The 2nd LR is deleted. Used for coalescing.
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// Note: the caller must make sure that L1 and L2 are distinct and both
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// LRs don't have suggested colors
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void LiveRangeInfo::unionAndUpdateLRs(LiveRange *const L1, LiveRange *L2)
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{
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assert( L1 != L2);
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L1->setUnion( L2 ); // add elements of L2 to L1
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ValueSet::iterator L2It;
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for( L2It = L2->begin() ; L2It != L2->end(); ++L2It) {
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//assert(( L1->getTypeID() == L2->getTypeID()) && "Merge:Different types");
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L1->add( *L2It ); // add the var in L2 to L1
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LiveRangeMap[ *L2It ] = L1; // now the elements in L2 should map to L1
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}
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// Now if LROfDef(L1) has a suggested color, it will remain.
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// But, if LROfUse(L2) has a suggested color, the new range
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// must have the same color.
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if(L2->hasSuggestedColor())
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L1->setSuggestedColor( L2->getSuggestedColor() );
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delete ( L2 ); // delete L2 as it is no longer needed
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}
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void LiveRangeInfo::constructLiveRanges()
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{
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if( DEBUG_RA)
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cout << "Consturcting Live Ranges ..." << endl;
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// first find the live ranges for all incoming args of the method since
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// those LRs start from the start of the method
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// get the argument list
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const Method::ArgumentListType& ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
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LiveRange * ArgRange = new LiveRange(); // creates a new LR and
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const Value *const Val = (const Value *) *ArgIt;
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assert( Val);
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ArgRange->add( Val ); // add the arg (def) to it
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LiveRangeMap[ Val ] = ArgRange;
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// create a temp machine op to find the register class of value
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//const MachineOperand Op(MachineOperand::MO_VirtualRegister);
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unsigned rcid = MRI.getRegClassIDOfValue( Val );
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ArgRange->setRegClass(RegClassList[ rcid ] );
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if( DEBUG_RA > 1) {
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cout << " adding LiveRange for argument ";
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printValue( (const Value *) *ArgIt); cout << endl;
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}
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}
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// Now suggest hardware registers for these method args
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MRI.suggestRegs4MethodArgs(Meth, *this);
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// Now find speical LLVM instructions (CALL, RET) and LRs in machine
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// instructions.
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // go thru BBs in random order
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// Now find all LRs for machine the instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator
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MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); MInstIterator++) {
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const MachineInstr * MInst = *MInstIterator;
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// Now if the machine instruction is a call/return instruction,
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// add it to CallRetInstrList for processing its implicit operands
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if( (TM.getInstrInfo()).isReturn( MInst->getOpCode()) ||
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(TM.getInstrInfo()).isCall( MInst->getOpCode()) )
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CallRetInstrList.push_back( MInst );
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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if( DEBUG_RA) {
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MachineOperand::MachineOperandType OpTyp =
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OpI.getMachineOperand().getOperandType();
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if ( OpTyp == MachineOperand::MO_CCRegister) {
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cout << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:";
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printValue( OpI.getMachineOperand().getVRegValue() );
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cout << endl;
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}
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}
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// create a new LR iff this operand is a def
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if( OpI.isDef() ) {
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const Value *const Def = *OpI;
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// Only instruction values are accepted for live ranges here
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if( Def->getValueType() != Value::InstructionVal ) {
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cout << "\n**%%Error: Def is not an instruction val. Def=";
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printValue( Def ); cout << endl;
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continue;
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}
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LiveRange *DefRange = LiveRangeMap[Def];
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// see LR already there (because of multiple defs)
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if( !DefRange) { // if it is not in LiveRangeMap
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DefRange = new LiveRange(); // creates a new live range and
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DefRange->add( Def ); // add the instruction (def) to it
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LiveRangeMap[ Def ] = DefRange; // update the map
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if( DEBUG_RA > 1) {
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cout << " creating a LR for def: ";
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printValue(Def); cout << endl;
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}
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// set the register class of the new live range
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//assert( RegClassList.size() );
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MachineOperand::MachineOperandType OpTy =
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OpI.getMachineOperand().getOperandType();
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bool isCC = ( OpTy == MachineOperand::MO_CCRegister);
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unsigned rcid = MRI.getRegClassIDOfValue(
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OpI.getMachineOperand().getVRegValue(), isCC );
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if(isCC && DEBUG_RA) {
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cout << "\a**created a LR for a CC reg:";
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printValue( OpI.getMachineOperand().getVRegValue() );
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}
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DefRange->setRegClass( RegClassList[ rcid ] );
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}
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else {
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DefRange->add( Def ); // add the opearand to def range
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// update the map - Operand points
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// to the merged set
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LiveRangeMap[ Def ] = DefRange;
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if( DEBUG_RA > 1) {
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cout << " added to an existing LR for def: ";
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printValue( Def ); cout << endl;
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}
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}
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} // if isDef()
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} // for all opereands in machine instructions
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} // for all machine instructions in the BB
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} // for all BBs in method
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// Now we have to suggest clors for call and return arg live ranges.
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// Also, if there are implicit defs (e.g., retun value of a call inst)
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// they must be added to the live range list
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suggestRegs4CallRets();
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if( DEBUG_RA)
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cout << "Initial Live Ranges constructed!" << endl;
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}
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// Suggest colors for call and return args.
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// Also create new LRs for implicit defs
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void LiveRangeInfo::suggestRegs4CallRets()
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{
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CallRetInstrListType::const_iterator It = CallRetInstrList.begin();
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for( ; It != CallRetInstrList.end(); ++It ) {
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const MachineInstr *MInst = *It;
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MachineOpCode OpCode = MInst->getOpCode();
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if( (TM.getInstrInfo()).isReturn(OpCode) )
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MRI.suggestReg4RetValue( MInst, *this);
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else if( (TM.getInstrInfo()).isCall( OpCode ) )
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MRI.suggestRegs4CallArgs( MInst, *this, RegClassList );
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else
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assert( 0 && "Non call/ret instr in CallRetInstrList" );
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}
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}
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void LiveRangeInfo::coalesceLRs()
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{
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/* Algorithm:
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for each BB in method
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for each machine instruction (inst)
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for each definition (def) in inst
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for each operand (op) of inst that is a use
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if the def and op are of the same register class
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if the def and op do not interfere //i.e., not simultaneously live
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if (degree(LR of def) + degree(LR of op)) <= # avail regs
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if both LRs do not have suggested colors
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merge2IGNodes(def, op) // i.e., merge 2 LRs
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*/
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if( DEBUG_RA)
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cout << endl << "Coalscing LRs ..." << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator
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MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr * MInst = *MInstIterator;
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if( DEBUG_RA > 1) {
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cout << " *Iterating over machine instr ";
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MInst->dump();
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cout << endl;
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}
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// iterate over MI operands to find defs
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for(MachineInstr::val_op_const_iterator DefI(MInst);!DefI.done();++DefI){
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if( DefI.isDef() ) { // iff this operand is a def
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LiveRange *const LROfDef = getLiveRangeForValue( *DefI );
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assert( LROfDef );
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RegClass *const RCOfDef = LROfDef->getRegClass();
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MachineInstr::val_op_const_iterator UseI(MInst);
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for( ; !UseI.done(); ++UseI){ // for all uses
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LiveRange *const LROfUse = getLiveRangeForValue( *UseI );
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if( ! LROfUse ) { // if LR of use is not found
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//don't warn about labels
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if (!((*UseI)->getType())->isLabelType() && DEBUG_RA) {
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cout<<" !! Warning: No LR for use "; printValue(*UseI);
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cout << endl;
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}
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continue; // ignore and continue
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}
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if( LROfUse == LROfDef) // nothing to merge if they are same
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continue;
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RegClass *const RCOfUse = LROfUse->getRegClass();
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if( RCOfDef == RCOfUse ) { // if the reg classes are the same
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if( ! RCOfDef->getInterference(LROfDef, LROfUse) ) {
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unsigned CombinedDegree =
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LROfDef->getUserIGNode()->getNumOfNeighbors() +
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LROfUse->getUserIGNode()->getNumOfNeighbors();
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if( CombinedDegree <= RCOfDef->getNumOfAvailRegs() ) {
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// if both LRs do not have suggested colors
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if( ! (LROfDef->hasSuggestedColor() &&
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LROfUse->hasSuggestedColor() ) ) {
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RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
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unionAndUpdateLRs(LROfDef, LROfUse);
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}
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} // if combined degree is less than # of regs
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} // if def and use do not interfere
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}// if reg classes are the same
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} // for all uses
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} // if def
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} // for all defs
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} // for all machine instructions
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} // for all BBs
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if( DEBUG_RA)
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cout << endl << "Coalscing Done!" << endl;
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}
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/*--------------------------- Debug code for printing ---------------*/
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void LiveRangeInfo::printLiveRanges()
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{
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LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator
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cout << endl << "Printing Live Ranges from Hash Map:" << endl;
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for( ; HMI != LiveRangeMap.end() ; HMI ++ ) {
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if( (*HMI).first && (*HMI).second ) {
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cout <<" "; printValue((*HMI).first); cout << "\t: ";
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((*HMI).second)->printSet(); cout << endl;
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}
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}
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}
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