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87773c318f
Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
866 B
LLVM
22 lines
866 B
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-neon < %s
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; The DAG combiner decided to use a vector load/store for this struct copy
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; previously. This probably shouldn't happen without NEON, but the most
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; important thing is that it compiles.
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define void @store_combine() nounwind {
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%src = alloca { double, double }, align 8
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%dst = alloca { double, double }, align 8
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%src.realp = getelementptr inbounds { double, double }* %src, i32 0, i32 0
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%src.real = load double* %src.realp
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%src.imagp = getelementptr inbounds { double, double }* %src, i32 0, i32 1
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%src.imag = load double* %src.imagp
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%dst.realp = getelementptr inbounds { double, double }* %dst, i32 0, i32 0
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%dst.imagp = getelementptr inbounds { double, double }* %dst, i32 0, i32 1
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store double %src.real, double* %dst.realp
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store double %src.imag, double* %dst.imagp
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ret void
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}
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