llvm-6502/lib/Target/Sparc
Rafael Espindola 26c8dcc692 Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 12:51:34 +00:00
..
MCTargetDesc Prune some includes 2012-03-27 07:54:11 +00:00
TargetInfo LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
CMakeLists.txt Fix up the CMake build for the new files added in r146960, they're 2011-12-20 08:42:11 +00:00
DelaySlotFiller.cpp Use uint16_t to store register overlaps to reduce static data. 2012-03-04 10:43:23 +00:00
FPMover.cpp Use uint16_t to store registers and opcode in static tables in the target specific backends. 2012-03-11 07:16:55 +00:00
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
Makefile Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
README.txt
Sparc.h Fix some leftover control reaches end of non-void function warnings. 2012-01-10 20:47:20 +00:00
Sparc.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcAsmPrinter.cpp Convert assert(0) to llvm_unreachable 2012-02-07 02:50:20 +00:00
SparcCallingConv.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcFrameLowering.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcFrameLowering.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcInstrFormats.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcInstrInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcInstrInfo.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
SparcInstrInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcISelDAGToDAG.cpp Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 2012-02-19 11:37:01 +00:00
SparcISelLowering.cpp Always compute all the bits in ComputeMaskedBits. 2012-04-04 12:51:34 +00:00
SparcISelLowering.h Always compute all the bits in ComputeMaskedBits. 2012-04-04 12:51:34 +00:00
SparcMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcMachineFunctionInfo.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SparcRegisterInfo.cpp Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
SparcRegisterInfo.h Use uint16_t to store registers in callee saved register tables to reduce size of static data. 2012-03-04 03:33:22 +00:00
SparcRegisterInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcSubtarget.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcTargetMachine.cpp Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
SparcTargetMachine.h TargetPassConfig: confine the MC configuration to TargetMachine. 2012-02-04 02:56:59 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support