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https://github.com/c64scene-ar/llvm-6502.git
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16fc5e9c0f
The expansion code does the same thing. Since the operands were not defined with the correct types, this has the side effect of fixing operand folding since the expanded pseudo would never use SGPRs or inline immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230072 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
4.3 KiB
LLVM
108 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare double @llvm.fabs.f64(double) #0
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; SI-LABEL: {{^}}fsub_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = fsub double %r0, %r1
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store double %r2, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_fabs_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|}}
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define void @fsub_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r1.fabs = call double @llvm.fabs.f64(double %r1) #0
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%r2 = fsub double %r0, %r1.fabs
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store double %r2, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_fabs_inv_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, -v\[[0-9]+:[0-9]+\]}}
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define void @fsub_fabs_inv_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r0.fabs = call double @llvm.fabs.f64(double %r0) #0
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%r2 = fsub double %r0.fabs, %r1
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store double %r2, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define void @s_fsub_f64(double addrspace(1)* %out, double %a, double %b) {
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%sub = fsub double %a, %b
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store double %sub, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_imm_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], 4.0, -s\[[0-9]+:[0-9]+\]}}
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define void @s_fsub_imm_f64(double addrspace(1)* %out, double %a, double %b) {
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%sub = fsub double 4.0, %a
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store double %sub, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_imm_inv_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -4.0, s\[[0-9]+:[0-9]+\]}}
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define void @s_fsub_imm_inv_f64(double addrspace(1)* %out, double %a, double %b) {
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%sub = fsub double %a, 4.0
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store double %sub, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_self_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}
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define void @s_fsub_self_f64(double addrspace(1)* %out, double %a) {
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%sub = fsub double %a, %a
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store double %sub, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_v2f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define void @fsub_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) {
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%sub = fsub <2 x double> %a, %b
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store <2 x double> %sub, <2 x double> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_v4f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define void @fsub_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x double> addrspace(1)* %in, i32 1
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%a = load <4 x double> addrspace(1)* %in
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%b = load <4 x double> addrspace(1)* %b_ptr
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%result = fsub <4 x double> %a, %b
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store <4 x double> %result, <4 x double> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_v4f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define void @s_fsub_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) {
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%result = fsub <4 x double> %a, %b
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store <4 x double> %result, <4 x double> addrspace(1)* %out, align 16
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ret void
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}
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attributes #0 = { nounwind readnone }
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