mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
3.6 KiB
LLVM
104 lines
3.6 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; The code generated by sdiv is long and complex and may frequently change.
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; The goal of this test is to make sure the ISel doesn't fail.
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;
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; This program was previously failing to compile when one of the selectcc
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; opcodes generated by the sdiv lowering was being legalized and optimized to:
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; selectcc Remainder -1, 0, -1, SETGT
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; This was fixed by adding an additional pattern in R600Instructions.td to
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; match this pattern with a CNDGE_INT.
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; FUNC-LABEL: {{^}}sdiv_i32:
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; EG: CF_END
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define void @sdiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in
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%den = load i32 addrspace(1) * %den_ptr
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%result = sdiv i32 %num, %den
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sdiv_i32_4:
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define void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%num = load i32 addrspace(1) * %in
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%result = sdiv i32 %num, 4
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; Multiply by a weird constant to make sure setIntDivIsCheap is
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; working.
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; FUNC-LABEL: {{^}}slow_sdiv_i32_3435:
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; SI: buffer_load_dword [[VAL:v[0-9]+]],
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; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b
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; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[VAL]], [[MAGIC]]
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; SI: v_add_i32
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; SI: v_lshrrev_b32
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; SI: v_ashrrev_i32
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; SI: v_add_i32
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; SI: buffer_store_dword
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; SI: s_endpgm
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define void @slow_sdiv_i32_3435(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%num = load i32 addrspace(1) * %in
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%result = sdiv i32 %num, 3435
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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define void @sdiv_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%den_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%num = load <2 x i32> addrspace(1) * %in
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%den = load <2 x i32> addrspace(1) * %den_ptr
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%result = sdiv <2 x i32> %num, %den
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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define void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%num = load <2 x i32> addrspace(1) * %in
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%result = sdiv <2 x i32> %num, <i32 4, i32 4>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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define void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%den_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%num = load <4 x i32> addrspace(1) * %in
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%den = load <4 x i32> addrspace(1) * %den_ptr
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%result = sdiv <4 x i32> %num, %den
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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define void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%num = load <4 x i32> addrspace(1) * %in
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%result = sdiv <4 x i32> %num, <i32 4, i32 4, i32 4, i32 4>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; Tests for 64-bit divide bypass.
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; define void @test_get_quotient(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %result = sdiv i64 %a, %b
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; define void @test_get_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %result = srem i64 %a, %b
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; define void @test_get_quotient_and_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %resultdiv = sdiv i64 %a, %b
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; %resultrem = srem i64 %a, %b
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; %result = add i64 %resultdiv, %resultrem
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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