mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-24 06:30:19 +00:00
18cba562c8
Changes to ARM unwind opcode assembler:
* Fix multiple .save or .vsave directives. Besides, the
order is preserved now.
* For the directives which will generate multiple opcodes,
such as ".save {r0-r11}", the order of the unwind opcode
is fixed now, i.e. the registers with less encoding value
are popped first.
* Fix the $sp offset calculation. Now, we can use the
.setfp, .pad, .save, and .vsave directives at any order.
Changes to test cases:
* Add test cases to check the order of multiple opcodes
for the .save directive.
* Fix the incorrect $sp offset in the test case. The
stack pointer offset specified in the test case was
incorrect. (Changed test cases: ehabi-mc-section.ll and
ehabi-mc.ll)
* The opcode to restore $sp are slightly reordered. The
behavior are not changed, and the new output is same
as the output of GNU as. (Changed test cases:
eh-directive-pad.s and eh-directive-setfp.s)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
344 lines
8.0 KiB
ArmAsm
344 lines
8.0 KiB
ArmAsm
@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
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@ RUN: | llvm-readobj -s -sd | FileCheck %s
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@ Check the .save directive
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@ The .save directive records the GPR registers which are pushed to the
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@ stack. There are 4 different unwind opcodes:
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@
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@ 0xB100: pop r[3:0]
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@ 0xA0: pop r[(4+x):4] @ r[4+x]-r[4] must be consecutive.
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@ 0xA8: pop r14, r[(4+x):4] @ r[4+x]-r[4] must be consecutive.
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@ 0x8000: pop r[15:4]
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@
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@ If register list specifed by .save directive is possible to be encoded
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@ by 0xA0 or 0xA8, then the assembler should prefer them over 0x8000.
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.syntax unified
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@-------------------------------------------------------------------------------
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@ TEST1
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@-------------------------------------------------------------------------------
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.section .TEST1
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.globl func1a
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.align 2
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.type func1a,%function
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.fnstart
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func1a:
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.save {r0}
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push {r0}
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pop {r0}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func1b
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.align 2
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.type func1b,%function
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.fnstart
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func1b:
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.save {r0, r1}
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push {r0, r1}
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pop {r0, r1}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func1c
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.align 2
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.type func1c,%function
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.fnstart
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func1c:
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.save {r0, r2}
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push {r0, r2}
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pop {r0, r2}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func1d
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.align 2
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.type func1d,%function
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.fnstart
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func1d:
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.save {r1, r2}
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push {r1, r2}
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pop {r1, r2}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func1e
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.align 2
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.type func1e,%function
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.fnstart
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func1e:
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.save {r0, r1, r2, r3}
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push {r0, r1, r2, r3}
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pop {r0, r1, r2, r3}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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@-------------------------------------------------------------------------------
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@ The assembler should emit 0xB000 unwind opcode.
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@-------------------------------------------------------------------------------
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@ CHECK: Section {
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@ CHECK: Name: .ARM.extab.TEST1
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@ CHECK: SectionData (
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@ CHECK: 0000: 00000000 B001B100 00000000 B003B100 |................|
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@ CHECK: 0010: 00000000 B005B100 00000000 B006B100 |................|
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@ CHECK: 0020: 00000000 B00FB100 |........|
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@ CHECK: )
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@ CHECK: }
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@-------------------------------------------------------------------------------
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@ TEST2
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@-------------------------------------------------------------------------------
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.section .TEST2
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.globl func2a
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.align 2
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.type func2a,%function
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.fnstart
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func2a:
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.save {r4}
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push {r4}
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pop {r4}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func2b
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.align 2
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.type func2b,%function
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.fnstart
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func2b:
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.save {r4, r5}
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push {r4, r5}
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pop {r4, r5}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func2c
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.align 2
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.type func2c,%function
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.fnstart
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func2c:
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.save {r4, r5, r6, r7, r8, r9, r10, r11}
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push {r4, r5, r6, r7, r8, r9, r10, r11}
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pop {r4, r5, r6, r7, r8, r9, r10, r11}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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@-------------------------------------------------------------------------------
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@ The assembler should emit 0xA0 unwind opcode.
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@-------------------------------------------------------------------------------
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@ CHECK: Section {
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@ CHECK: Name: .ARM.extab.TEST2
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@ CHECK: SectionData (
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@ CHECK: 0000: 00000000 B0B0A000 00000000 B0B0A100 |................|
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@ CHECK: 0010: 00000000 B0B0A700 |........|
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@ CHECK: )
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@ CHECK: }
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@-------------------------------------------------------------------------------
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@ TEST3
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@-------------------------------------------------------------------------------
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.section .TEST3
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.globl func3a
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.align 2
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.type func3a,%function
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.fnstart
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func3a:
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.save {r4, r14}
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push {r4, r14}
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pop {r4, r14}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func3b
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.align 2
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.type func3b,%function
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.fnstart
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func3b:
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.save {r4, r5, r14}
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push {r4, r5, r14}
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pop {r4, r5, r14}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func3c
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.align 2
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.type func3c,%function
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.fnstart
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func3c:
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.save {r4, r5, r6, r7, r8, r9, r10, r11, r14}
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push {r4, r5, r6, r7, r8, r9, r10, r11, r14}
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pop {r4, r5, r6, r7, r8, r9, r10, r11, r14}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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@-------------------------------------------------------------------------------
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@ The assembler should emit 0xA8 unwind opcode.
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@-------------------------------------------------------------------------------
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@ CHECK: Section {
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@ CHECK: Name: .ARM.extab.TEST3
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@ CHECK: SectionData (
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@ CHECK: 0000: 00000000 B0B0A800 00000000 B0B0A900 |................|
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@ CHECK: 0010: 00000000 B0B0AF00 |........|
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@ CHECK: )
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@ CHECK: }
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@-------------------------------------------------------------------------------
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@ TEST4
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@-------------------------------------------------------------------------------
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.section .TEST4
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.globl func4a
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.align 2
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.type func4a,%function
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.fnstart
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func4a:
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.save {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
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push {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
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pop {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func4b
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.align 2
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.type func4b,%function
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.fnstart
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func4b:
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@ Note: r7 is missing intentionally.
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.save {r4, r5, r6, r8, r9, r10, r11}
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push {r4, r5, r6, r8, r9, r10, r11}
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pop {r4, r5, r6, r8, r9, r10, r11}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func4c
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.align 2
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.type func4c,%function
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.fnstart
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func4c:
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@ Note: r7 is missing intentionally.
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.save {r4, r5, r6, r8, r9, r10, r11, r14}
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push {r4, r5, r6, r8, r9, r10, r11, r14}
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pop {r4, r5, r6, r8, r9, r10, r11, r14}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func4d
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.align 2
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.type func4d,%function
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.fnstart
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func4d:
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@ Note: The register list is not start with r4.
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.save {r5, r6, r7}
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push {r5, r6, r7}
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pop {r5, r6, r7}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func4e
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.align 2
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.type func4e,%function
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.fnstart
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func4e:
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@ Note: The register list is not start with r4.
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.save {r5, r6, r7, r14}
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push {r5, r6, r7, r14}
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pop {r5, r6, r7, r14}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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@-------------------------------------------------------------------------------
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@ The assembler should emit 0x8000 unwind opcode.
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@-------------------------------------------------------------------------------
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@ CHECK: Section {
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@ CHECK: Name: .ARM.extab.TEST4
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@ CHECK: SectionData (
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@ CHECK: 0000: 00000000 B0FF8500 00000000 B0F78000 |................|
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@ CHECK: 0010: 00000000 B0F78400 00000000 B00E8000 |................|
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@ CHECK: 0020: 00000000 B00E8400 |........|
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@ CHECK: )
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@ CHECK: }
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@-------------------------------------------------------------------------------
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@ TEST5
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@-------------------------------------------------------------------------------
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.section .TEST5
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.globl func5a
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.align 2
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.type func5a,%function
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.fnstart
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func5a:
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.save {r0, r1, r2, r3, r4, r5, r6}
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push {r0, r1, r2, r3, r4, r5, r6}
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pop {r0, r1, r2, r3, r4, r5, r6}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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.globl func5b
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.align 2
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.type func5b,%function
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.fnstart
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func5b:
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.save {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
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pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
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bx lr
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.personality __gxx_personality_v0
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.handlerdata
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.fnend
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@-------------------------------------------------------------------------------
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@ Check the order of unwind opcode to pop registers.
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@ 0xB10F "pop {r0-r3}" should be emitted before 0xA2 "pop {r4-r6}".
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@ 0xB10F "pop {r0-r3}" should be emitted before 0x85FF "pop {r4-r12, r14}".
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@-------------------------------------------------------------------------------
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@ CHECK: Section {
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@ CHECK: Name: .ARM.extab.TEST5
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@ CHECK: SectionData (
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@ CHECK: 0000: 00000000 A20FB100 00000000 850FB101 |................|
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@ CHECK: 0010: B0B0B0FF |....|
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@ CHECK: )
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@ CHECK: }
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