Evan Cheng 5792f51e12 Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values. ... Also, if the compare is the only use, LSR would place the iv increment instruction before the compare instead in the latch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71485 91177308-0d34-0410-b5e6-96231b3b80d8		2009-05-11 22:33:01 +00:00
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Alpha
ARM	Fix pr4100. Do not remove no-op copies when they are dead. The register	2009-05-07 23:47:03 +00:00
CBackend
CellSPU	Revert 67132. This is breaking some objective-c apps.	2009-03-25 20:20:11 +00:00
CPP	Fix code emission for conditional branches.	2009-05-04 19:10:38 +00:00
Generic	Disable the load-shrinking optimization from looking at	2009-04-29 03:45:07 +00:00
IA64
Mips
MSP430	Add MSP430 test for PR4136	2009-05-10 14:48:36 +00:00
PowerPC	Second attempt:	2009-04-29 00:15:41 +00:00
SPARC
X86	Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values.	2009-05-11 22:33:01 +00:00
XCore	testcase for PR3898	2009-04-18 20:49:22 +00:00