Chad Rosier 57b2997966 Add support for Thumb load/stores with negative offsets. ...

rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8

2011-11-14 20:22:27 +00:00

..

ARM

Add support for Thumb load/stores with negative offsets.

2011-11-14 20:22:27 +00:00

CBackend

Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported

2011-09-26 06:44:27 +00:00

CellSPU

Remove histogram tests.

2011-11-12 22:39:40 +00:00

CPP

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Generic

Remove the the test which checks the saving of a vector of booleans into memory.

2011-10-16 19:06:06 +00:00

MBlaze

Change the default scheduler from Latency to ILP, since Latency

2011-10-24 17:45:02 +00:00

Mips

Reapply r143206, with fixes. Disallow physical register lifetimes

2011-11-03 21:49:52 +00:00

MSP430

Remove the explicit request for "Latency" scheduling from MSP430,

2011-10-24 17:53:16 +00:00

PowerPC

test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now.

2011-10-28 23:11:03 +00:00

PTX

allow non-device function calls in PTX when natively handling device-side printf

2011-11-11 14:45:12 +00:00

SPARC

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Thumb

Reapply r143206, with fixes. Disallow physical register lifetimes

2011-11-03 21:49:52 +00:00

Thumb2

Linear scan is going away.

2011-11-12 22:39:34 +00:00

X86

Teach two-address pass to re-schedule two-address instructions (or the kill

2011-11-14 19:48:55 +00:00

XCore

Don't fold negative offsets into cp / dp accesses to avoid relocation errors.

2011-11-01 11:31:53 +00:00