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priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
215 lines
7.4 KiB
C++
215 lines
7.4 KiB
C++
//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the SPARC target.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcISelLowering.h"
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#include "SparcTargetMachine.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class SparcDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const SparcSubtarget &Subtarget;
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public:
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explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
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: SelectionDAGISel(*TM.getTargetLowering()),
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Subtarget(TM.getSubtarget<SparcSubtarget>()) {
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}
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SDNode *Select(SDValue Op);
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "SPARC DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "SparcGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void SparcDAGToDAGISel::InstructionSelect() {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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SelectRoot(*CurDAG);
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CurDAG->RemoveDeadNodes();
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}
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bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Offset) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_simm13(CN)) {
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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// Constant offset from frame ref.
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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return true;
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}
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}
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(1);
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
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SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).getNode()))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
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Addr.getOperand(1).getOpcode() == SPISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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return true;
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}
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R1 = Addr;
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R2 = CurDAG->getRegister(SP::G0, MVT::i32);
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return true;
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}
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SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
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SDNode *N = Op.getNode();
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if (N->isMachineOpcode())
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return NULL; // Already selected.
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switch (N->getOpcode()) {
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default: break;
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case ISD::SDIV:
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case ISD::UDIV: {
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// FIXME: should use a custom expander to expose the SRA to the dag.
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SDValue DivLHS = N->getOperand(0);
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SDValue DivRHS = N->getOperand(1);
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// Set the Y register to the high-part.
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SDValue TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, MVT::i32)), 0);
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} else {
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TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
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}
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TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
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CurDAG->getRegister(SP::G0, MVT::i32)), 0);
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
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TopPart);
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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// FIXME: Handle mul by immediate.
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SDValue MulLHS = N->getOperand(0);
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SDValue MulRHS = N->getOperand(1);
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unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
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SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
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MulLHS, MulRHS);
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// The high part is in the Y register.
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return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
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return NULL;
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}
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}
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return SelectCode(Op);
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool
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SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectADDRrr(Op, Op, Op0, Op1))
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SelectADDRri(Op, Op, Op0, Op1);
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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/// createSparcISelDag - This pass converts a legalized DAG into a
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/// SPARC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
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return new SparcDAGToDAGISel(TM);
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}
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