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https://github.com/c64scene-ar/llvm-6502.git
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57edb9588b
Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201237 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
2.7 KiB
LLVM
74 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - -no-integrated-as | FileCheck %s
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; C code this came from
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;bool cas(float volatile *p, float *expected, float desired) {
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; bool success;
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; __asm__ __volatile__("lock; cmpxchg %[desired], %[mem]; "
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; "mov %[expected], %[expected_out]; "
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; "sete %[success]"
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; : [success] "=a" (success),
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; [expected_out] "=rm" (*expected)
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; : [expected] "a" (*expected),
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; [desired] "q" (desired),
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; [mem] "m" (*p)
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; : "memory", "cc");
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; return success;
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;}
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define zeroext i1 @cas(float* %p, float* %expected, float %desired) nounwind {
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entry:
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%p.addr = alloca float*, align 8
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%expected.addr = alloca float*, align 8
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%desired.addr = alloca float, align 4
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%success = alloca i8, align 1
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store float* %p, float** %p.addr, align 8
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store float* %expected, float** %expected.addr, align 8
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store float %desired, float* %desired.addr, align 4
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%0 = load float** %expected.addr, align 8
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%1 = load float** %expected.addr, align 8
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%2 = load float* %1, align 4
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%3 = load float* %desired.addr, align 4
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%4 = load float** %p.addr, align 8
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%5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(float* %0, float %2, float %3, float* %4) nounwind
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store i8 %5, i8* %success, align 1
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%6 = load i8* %success, align 1
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%tobool = trunc i8 %6 to i1
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ret i1 %tobool
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}
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; CHECK: @cas
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; Make sure we're emitting a move from eax.
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; CHECK: #APP
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; CHECK-NEXT: lock;{{.*}}mov %eax,{{.*}}
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; CHECK-NEXT: #NO_APP
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define zeroext i1 @cas2(i8* %p, i8* %expected, i1 zeroext %desired) nounwind {
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entry:
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%p.addr = alloca i8*, align 8
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%expected.addr = alloca i8*, align 8
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%desired.addr = alloca i8, align 1
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%success = alloca i8, align 1
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store i8* %p, i8** %p.addr, align 8
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store i8* %expected, i8** %expected.addr, align 8
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%frombool = zext i1 %desired to i8
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store i8 %frombool, i8* %desired.addr, align 1
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%0 = load i8** %expected.addr, align 8
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%1 = load i8** %expected.addr, align 8
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%2 = load i8* %1, align 1
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%tobool = trunc i8 %2 to i1
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%3 = load i8* %desired.addr, align 1
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%tobool1 = trunc i8 %3 to i1
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%4 = load i8** %p.addr, align 8
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%5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i8* %0, i1 %tobool, i1 %tobool1, i8* %4) nounwind
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store i8 %5, i8* %success, align 1
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%6 = load i8* %success, align 1
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%tobool2 = trunc i8 %6 to i1
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ret i1 %tobool2
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}
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; CHECK: @cas2
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; Make sure we're emitting a move from %al here.
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; CHECK: #APP
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; CHECK-NEXT: lock;{{.*}}mov %al,{{.*}}
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; CHECK-NEXT: #NO_APP
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