mirror of
https://github.com/c64scene-ar/llvm-6502.git
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57f0db833d
them are generic changes. - Use the "fast" flag that's already being passed into the asm printers instead of shoving it into the DwarfWriter. - Instead of calling "MI->getParent()->getParent()" for every MI, set the machine function when calling "runOnMachineFunction" in the asm printers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
265 lines
9.3 KiB
C++
265 lines
9.3 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetAsmInfo.h"
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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using namespace llvm;
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/// X86TargetMachineModule - Note that this is used on hosts that cannot link
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/// in a library unless there are references into the library. In particular,
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/// it seems that it is not possible to get things to work on Win32 without
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/// this. Though it is unused, do not remove it.
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extern "C" int X86TargetMachineModule;
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int X86TargetMachineModule = 0;
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// Register the target.
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static RegisterTarget<X86_32TargetMachine>
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X("x86", "32-bit X86: Pentium-Pro and above");
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static RegisterTarget<X86_64TargetMachine>
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Y("x86-64", "64-bit X86: EM64T and AMD64");
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// No assembler printer by default
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X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0;
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const TargetAsmInfo *X86TargetMachine::createTargetAsmInfo() const {
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if (Subtarget.isFlavorIntel())
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return new X86WinTargetAsmInfo(*this);
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else
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switch (Subtarget.TargetType) {
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case X86Subtarget::isDarwin:
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return new X86DarwinTargetAsmInfo(*this);
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case X86Subtarget::isELF:
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return new X86ELFTargetAsmInfo(*this);
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case X86Subtarget::isMingw:
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case X86Subtarget::isCygwin:
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return new X86COFFTargetAsmInfo(*this);
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case X86Subtarget::isWindows:
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return new X86WinTargetAsmInfo(*this);
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default:
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return new X86GenericTargetAsmInfo(*this);
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}
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}
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unsigned X86_32TargetMachine::getJITMatchQuality() {
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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return 10;
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#endif
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return 0;
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}
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unsigned X86_64TargetMachine::getJITMatchQuality() {
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#if defined(__x86_64__) || defined(_M_AMD64)
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return 10;
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#endif
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return 0;
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}
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unsigned X86_32TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "i[3-9]86-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
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TT[4] == '-' && TT[1] - '3' < 6)
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return 20;
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// If the target triple is something non-X86, we don't match.
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if (!TT.empty()) return 0;
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if (M.getEndianness() == Module::LittleEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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unsigned X86_64TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "x86_64-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 7 && TT[0] == 'x' && TT[1] == '8' && TT[2] == '6' &&
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TT[3] == '_' && TT[4] == '6' && TT[5] == '4' && TT[6] == '-')
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return 20;
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// We strongly match "amd64-*".
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if (TT.size() >= 6 && TT[0] == 'a' && TT[1] == 'm' && TT[2] == 'd' &&
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TT[3] == '6' && TT[4] == '4' && TT[5] == '-')
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return 20;
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// If the target triple is something non-X86-64, we don't match.
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if (!TT.empty()) return 0;
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if (M.getEndianness() == Module::LittleEndian &&
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M.getPointerSize() == Module::Pointer64)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS)
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: X86TargetMachine(M, FS, false) {
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}
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X86_64TargetMachine::X86_64TargetMachine(const Module &M, const std::string &FS)
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: X86TargetMachine(M, FS, true) {
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}
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/// X86TargetMachine ctor - Create an ILP32 architecture model
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///
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X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
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bool is64Bit)
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: Subtarget(M, FS, is64Bit),
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DataLayout(Subtarget.getDataLayout()),
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FrameInfo(TargetFrameInfo::StackGrowsDown,
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Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4),
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InstrInfo(*this), JITInfo(*this), TLInfo(*this) {
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DefRelocModel = getRelocationModel();
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// FIXME: Correctly select PIC model for Win64 stuff
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if (getRelocationModel() == Reloc::Default) {
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if (Subtarget.isTargetDarwin() ||
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(Subtarget.isTargetCygMing() && !Subtarget.isTargetWin64()))
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setRelocationModel(Reloc::DynamicNoPIC);
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else
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setRelocationModel(Reloc::Static);
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}
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// ELF doesn't have a distinct dynamic-no-PIC model. Dynamic-no-PIC
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// is defined as a model for code which may be used in static or
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// dynamic executables but not necessarily a shared library. On ELF
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// implement this by using the Static model.
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if (Subtarget.isTargetELF() &&
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getRelocationModel() == Reloc::DynamicNoPIC)
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setRelocationModel(Reloc::Static);
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if (Subtarget.is64Bit()) {
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// No DynamicNoPIC support under X86-64.
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if (getRelocationModel() == Reloc::DynamicNoPIC)
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setRelocationModel(Reloc::PIC_);
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// Default X86-64 code model is small.
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if (getCodeModel() == CodeModel::Default)
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setCodeModel(CodeModel::Small);
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}
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if (Subtarget.isTargetCygMing())
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Subtarget.setPICStyle(PICStyles::WinPIC);
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else if (Subtarget.isTargetDarwin()) {
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if (Subtarget.is64Bit())
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Subtarget.setPICStyle(PICStyles::RIPRel);
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else
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Subtarget.setPICStyle(PICStyles::Stub);
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} else if (Subtarget.isTargetELF()) {
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if (Subtarget.is64Bit())
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Subtarget.setPICStyle(PICStyles::RIPRel);
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else
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Subtarget.setPICStyle(PICStyles::GOT);
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}
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
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// Install an instruction selector.
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PM.add(createX86ISelDag(*this, Fast));
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// If we're using Fast-ISel, clean up the mess.
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if (EnableFastISel)
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PM.add(createDeadMachineInstructionElimPass());
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// Install a pass to insert x87 FP_REG_KILL instructions, as needed.
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PM.add(createX87FPRegKillInserterPass());
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return false;
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}
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bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool Fast) {
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// Calculate and set max stack object alignment early, so we can decide
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// whether we will need stack realignment (and thus FP).
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PM.add(createX86MaxStackAlignmentCalculatorPass());
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return false; // -print-machineinstr shouldn't print after this.
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}
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bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool Fast) {
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PM.add(createX86FloatingPointStackifierPass());
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return true; // -print-machineinstr should print after this.
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}
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bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
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raw_ostream &Out) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(Out, *this, Fast));
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return false;
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}
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
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bool DumpAsm, MachineCodeEmitter &MCE) {
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// FIXME: Move this to TargetJITInfo!
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// On Darwin, do not override 64-bit setting made in X86TargetMachine().
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if (DefRelocModel == Reloc::Default &&
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(!Subtarget.isTargetDarwin() || !Subtarget.is64Bit()))
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setRelocationModel(Reloc::Static);
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// 64-bit JIT places everything in the same buffer except external functions.
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// On Darwin, use small code model but hack the call instruction for
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// externals. Elsewhere, do not assume globals are in the lower 4G.
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if (Subtarget.is64Bit()) {
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if (Subtarget.isTargetDarwin())
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setCodeModel(CodeModel::Small);
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else
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setCodeModel(CodeModel::Large);
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}
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PM.add(createX86CodeEmitterPass(*this, MCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this, Fast));
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}
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return false;
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}
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bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
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bool DumpAsm, MachineCodeEmitter &MCE) {
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PM.add(createX86CodeEmitterPass(*this, MCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this, Fast));
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}
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return false;
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}
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/// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
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/// RIP-relative on this machine, taking into consideration the relocation
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/// model and subtarget. RIP-relative addresses cannot have a separate
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/// base or index register.
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bool X86TargetMachine::symbolicAddressesAreRIPRel() const {
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return getRelocationModel() != Reloc::Static &&
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Subtarget.isPICStyleRIPRel();
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}
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