mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
76020ed6f3
Filling no-ops is done just before emitting of assembly, when the instruction stream is final. No-ops are inserted to align the instructions so the dual-issue of the pipeline is utilized. This speeds up generated code with a minimum of 1% on a select set of algorithms. This pass may be redundant if the instruction scheduler and all subsequent passes that modify the instruction stream (prolog+epilog inserter, register scavenger, are there others?) are made aware of the instruction alignments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123226 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
822 B
CMake
28 lines
822 B
CMake
set(LLVM_TARGET_DEFINITIONS SPU.td)
|
|
|
|
tablegen(SPUGenInstrNames.inc -gen-instr-enums)
|
|
tablegen(SPUGenRegisterNames.inc -gen-register-enums)
|
|
tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
|
|
tablegen(SPUGenCodeEmitter.inc -gen-emitter)
|
|
tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header)
|
|
tablegen(SPUGenRegisterInfo.inc -gen-register-desc)
|
|
tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
|
|
tablegen(SPUGenDAGISel.inc -gen-dag-isel)
|
|
tablegen(SPUGenSubtarget.inc -gen-subtarget)
|
|
tablegen(SPUGenCallingConv.inc -gen-callingconv)
|
|
|
|
add_llvm_target(CellSPUCodeGen
|
|
SPUAsmPrinter.cpp
|
|
SPUHazardRecognizers.cpp
|
|
SPUInstrInfo.cpp
|
|
SPUISelDAGToDAG.cpp
|
|
SPUISelLowering.cpp
|
|
SPUFrameLowering.cpp
|
|
SPUMCAsmInfo.cpp
|
|
SPURegisterInfo.cpp
|
|
SPUSubtarget.cpp
|
|
SPUTargetMachine.cpp
|
|
SPUSelectionDAGInfo.cpp
|
|
SPUNopFiller.cpp
|
|
)
|