mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 03:30:28 +00:00
f03bb260c9
of the instruction. Note that this change affects the existing non-atomic load and store instructions; the parser now accepts both forms, and the change is noted in the release notes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137527 91177308-0d34-0410-b5e6-96231b3b80d8
151 lines
3.4 KiB
LLVM
151 lines
3.4 KiB
LLVM
; RUN: opt < %s -basicaa -licm -S | FileCheck %s
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target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
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@X = global i32 7 ; <i32*> [#uses=4]
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define void @test1(i32 %i) {
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Entry:
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br label %Loop
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; CHECK: @test1
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; CHECK: Entry:
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; CHECK-NEXT: load i32* @X
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; CHECK-NEXT: br label %Loop
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Loop: ; preds = %Loop, %0
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%j = phi i32 [ 0, %Entry ], [ %Next, %Loop ] ; <i32> [#uses=1]
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%x = load i32* @X ; <i32> [#uses=1]
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%x2 = add i32 %x, 1 ; <i32> [#uses=1]
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store i32 %x2, i32* @X
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%Next = add i32 %j, 1 ; <i32> [#uses=2]
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%cond = icmp eq i32 %Next, 0 ; <i1> [#uses=1]
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br i1 %cond, label %Out, label %Loop
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Out:
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ret void
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; CHECK: Out:
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; CHECK-NEXT: store i32 %x2, i32* @X
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; CHECK-NEXT: ret void
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}
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define void @test2(i32 %i) {
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Entry:
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br label %Loop
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; CHECK: @test2
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; CHECK: Entry:
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; CHECK-NEXT: %.promoted = load i32* getelementptr inbounds (i32* @X, i64 1)
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; CHECK-NEXT: br label %Loop
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Loop: ; preds = %Loop, %0
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%X1 = getelementptr i32* @X, i64 1 ; <i32*> [#uses=1]
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%A = load i32* %X1 ; <i32> [#uses=1]
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%V = add i32 %A, 1 ; <i32> [#uses=1]
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%X2 = getelementptr i32* @X, i64 1 ; <i32*> [#uses=1]
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store i32 %V, i32* %X2
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br i1 false, label %Loop, label %Exit
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Exit: ; preds = %Loop
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ret void
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; CHECK: Exit:
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; CHECK-NEXT: store i32 %V, i32* getelementptr inbounds (i32* @X, i64 1)
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; CHECK-NEXT: ret void
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}
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define void @test3(i32 %i) {
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; CHECK: @test3
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br label %Loop
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Loop:
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; Should not promote this to a register
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%x = volatile load i32* @X
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%x2 = add i32 %x, 1
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store i32 %x2, i32* @X
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br i1 true, label %Out, label %Loop
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; CHECK: Loop:
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; CHECK-NEXT: load volatile
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Out: ; preds = %Loop
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ret void
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}
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; PR8041
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define void @test4(i8* %x, i8 %n) {
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; CHECK: @test4
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%handle1 = alloca i8*
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%handle2 = alloca i8*
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store i8* %x, i8** %handle1
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br label %loop
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loop:
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%tmp = getelementptr i8* %x, i64 8
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store i8* %tmp, i8** %handle2
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br label %subloop
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subloop:
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%count = phi i8 [ 0, %loop ], [ %nextcount, %subloop ]
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%offsetx2 = load i8** %handle2
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store i8 %n, i8* %offsetx2
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%newoffsetx2 = getelementptr i8* %offsetx2, i64 -1
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store i8* %newoffsetx2, i8** %handle2
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%nextcount = add i8 %count, 1
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%innerexitcond = icmp sge i8 %nextcount, 8
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br i1 %innerexitcond, label %innerexit, label %subloop
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; Should have promoted 'handle2' accesses.
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; CHECK: subloop:
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; CHECK-NEXT: phi i8* [
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; CHECK-NEXT: %count = phi i8 [
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; CHECK-NEXT: store i8 %n
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; CHECK-NOT: store
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; CHECK: br i1
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innerexit:
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%offsetx1 = load i8** %handle1
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%val = load i8* %offsetx1
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%cond = icmp eq i8 %val, %n
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br i1 %cond, label %exit, label %loop
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; Should not have promoted offsetx1 loads.
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; CHECK: innerexit:
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; CHECK: %val = load i8* %offsetx1
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; CHECK: %cond = icmp eq i8 %val, %n
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; CHECK: br i1 %cond, label %exit, label %loop
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exit:
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ret void
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}
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define void @test5(i32 %i, i32** noalias %P2) {
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Entry:
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br label %Loop
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; CHECK: @test5
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; CHECK: Entry:
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; CHECK-NEXT: load i32* @X
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; CHECK-NEXT: br label %Loop
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Loop: ; preds = %Loop, %0
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%j = phi i32 [ 0, %Entry ], [ %Next, %Loop ] ; <i32> [#uses=1]
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%x = load i32* @X ; <i32> [#uses=1]
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%x2 = add i32 %x, 1 ; <i32> [#uses=1]
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store i32 %x2, i32* @X
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volatile store i32* @X, i32** %P2
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%Next = add i32 %j, 1 ; <i32> [#uses=2]
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%cond = icmp eq i32 %Next, 0 ; <i1> [#uses=1]
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br i1 %cond, label %Out, label %Loop
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Out:
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ret void
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; CHECK: Out:
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; CHECK-NEXT: store i32 %x2, i32* @X
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; CHECK-NEXT: ret void
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}
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