mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
77859c9e9c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219002 91177308-0d34-0410-b5e6-96231b3b80d8
443 lines
16 KiB
C++
443 lines
16 KiB
C++
//===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// The AMDGPUAsmPrinter is used to print both assembly string and also binary
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/// code. When passed an MCAsmStreamer it prints assembly and when passed
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/// an MCObjectStreamer it outputs binary code.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUAsmPrinter.h"
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "R600Defines.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "SIDefines.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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using namespace llvm;
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// TODO: This should get the default rounding mode from the kernel. We just set
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// the default here, but this could change if the OpenCL rounding mode pragmas
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// are used.
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//
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// The denormal mode here should match what is reported by the OpenCL runtime
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// for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
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// can also be override to flush with the -cl-denorms-are-zero compiler flag.
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//
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// AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
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// precision, and leaves single precision to flush all and does not report
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// CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
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// CL_FP_DENORM for both.
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//
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// FIXME: It seems some instructions do not support single precision denormals
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// regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
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// and sin_f32, cos_f32 on most parts).
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// We want to use these instructions, and using fp32 denormals also causes
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// instructions to run at the double precision rate for the device so it's
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// probably best to just report no single precision denormals.
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static uint32_t getFPMode(const MachineFunction &F) {
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const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
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// TODO: Is there any real use for the flush in only / flush out only modes?
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uint32_t FP32Denormals =
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ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
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uint32_t FP64Denormals =
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ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
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return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
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FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
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FP_DENORM_MODE_SP(FP32Denormals) |
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FP_DENORM_MODE_DP(FP64Denormals);
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}
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static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
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MCStreamer &Streamer) {
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return new AMDGPUAsmPrinter(tm, Streamer);
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}
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extern "C" void LLVMInitializeR600AsmPrinter() {
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TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
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}
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AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {
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DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
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}
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void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
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// This label is used to mark the end of the .text section.
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const TargetLoweringObjectFile &TLOF = getObjFileLowering();
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OutStreamer.SwitchSection(TLOF.getTextSection());
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MCSymbol *EndOfTextLabel =
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OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
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OutStreamer.EmitLabel(EndOfTextLabel);
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}
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bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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// The starting address of all shader programs must be 256 bytes aligned.
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MF.setAlignment(8);
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SetupMachineFunction(MF);
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EmitFunctionHeader();
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MCContext &Context = getObjFileLowering().getContext();
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const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
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ELF::SHT_PROGBITS, 0,
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SectionKind::getReadOnly());
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OutStreamer.SwitchSection(ConfigSection);
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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SIProgramInfo KernelInfo;
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if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
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getSIProgramInfo(KernelInfo, MF);
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EmitProgramInfoSI(MF, KernelInfo);
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} else {
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EmitProgramInfoR600(MF);
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}
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DisasmLines.clear();
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HexLines.clear();
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DisasmLineMaxLen = 0;
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OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
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EmitFunctionBody();
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if (isVerbose()) {
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const MCSectionELF *CommentSection
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= Context.getELFSection(".AMDGPU.csdata",
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ELF::SHT_PROGBITS, 0,
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SectionKind::getReadOnly());
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OutStreamer.SwitchSection(CommentSection);
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if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
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OutStreamer.emitRawComment(" Kernel info:", false);
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OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
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false);
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OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
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false);
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OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
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false);
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OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
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false);
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OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
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false);
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OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
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false);
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} else {
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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OutStreamer.emitRawComment(
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Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
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}
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}
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if (STM.dumpCode()) {
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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MF.dump();
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#endif
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if (DisasmEnabled) {
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OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
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ELF::SHT_NOTE, 0,
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SectionKind::getReadOnly()));
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for (size_t i = 0; i < DisasmLines.size(); ++i) {
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std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
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Comment += " ; " + HexLines[i] + "\n";
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OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
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OutStreamer.EmitBytes(StringRef(Comment));
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}
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}
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}
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return false;
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}
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void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
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unsigned MaxGPR = 0;
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bool killPixel = false;
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const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
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TM.getSubtargetImpl()->getRegisterInfo());
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const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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if (MI.getOpcode() == AMDGPU::KILLGT)
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killPixel = true;
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unsigned numOperands = MI.getNumOperands();
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for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
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const MachineOperand &MO = MI.getOperand(op_idx);
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if (!MO.isReg())
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continue;
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unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
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// Register with value > 127 aren't GPR
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if (HWReg > 127)
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continue;
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MaxGPR = std::max(MaxGPR, HWReg);
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}
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}
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}
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unsigned RsrcReg;
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if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
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// Evergreen / Northern Islands
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switch (MFI->getShaderType()) {
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default: // Fall through
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case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
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case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
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case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
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case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
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}
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} else {
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// R600 / R700
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switch (MFI->getShaderType()) {
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default: // Fall through
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case ShaderType::GEOMETRY: // Fall through
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case ShaderType::COMPUTE: // Fall through
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case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
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case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
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}
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}
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OutStreamer.EmitIntValue(RsrcReg, 4);
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OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
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S_STACK_SIZE(MFI->StackSize), 4);
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OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
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OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
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if (MFI->getShaderType() == ShaderType::COMPUTE) {
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OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
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OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
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}
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}
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void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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const MachineFunction &MF) const {
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uint64_t CodeSize = 0;
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unsigned MaxSGPR = 0;
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unsigned MaxVGPR = 0;
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bool VCCUsed = false;
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bool FlatUsed = false;
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const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
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TM.getSubtargetImpl()->getRegisterInfo());
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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// TODO: CodeSize should account for multiple functions.
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CodeSize += MI.getDesc().Size;
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unsigned numOperands = MI.getNumOperands();
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for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
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const MachineOperand &MO = MI.getOperand(op_idx);
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unsigned width = 0;
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bool isSGPR = false;
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if (!MO.isReg()) {
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continue;
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}
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unsigned reg = MO.getReg();
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if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
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reg == AMDGPU::VCC_HI) {
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VCCUsed = true;
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continue;
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} else if (reg == AMDGPU::FLAT_SCR ||
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reg == AMDGPU::FLAT_SCR_LO ||
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reg == AMDGPU::FLAT_SCR_HI) {
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FlatUsed = true;
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continue;
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}
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switch (reg) {
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default: break;
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case AMDGPU::SCC:
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case AMDGPU::EXEC:
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case AMDGPU::M0:
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continue;
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}
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if (AMDGPU::SReg_32RegClass.contains(reg)) {
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isSGPR = true;
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width = 1;
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} else if (AMDGPU::VReg_32RegClass.contains(reg)) {
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isSGPR = false;
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width = 1;
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} else if (AMDGPU::SReg_64RegClass.contains(reg)) {
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isSGPR = true;
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width = 2;
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} else if (AMDGPU::VReg_64RegClass.contains(reg)) {
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isSGPR = false;
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width = 2;
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} else if (AMDGPU::VReg_96RegClass.contains(reg)) {
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isSGPR = false;
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width = 3;
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} else if (AMDGPU::SReg_128RegClass.contains(reg)) {
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isSGPR = true;
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width = 4;
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} else if (AMDGPU::VReg_128RegClass.contains(reg)) {
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isSGPR = false;
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width = 4;
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} else if (AMDGPU::SReg_256RegClass.contains(reg)) {
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isSGPR = true;
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width = 8;
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} else if (AMDGPU::VReg_256RegClass.contains(reg)) {
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isSGPR = false;
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width = 8;
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} else if (AMDGPU::SReg_512RegClass.contains(reg)) {
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isSGPR = true;
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width = 16;
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} else if (AMDGPU::VReg_512RegClass.contains(reg)) {
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isSGPR = false;
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width = 16;
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} else {
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llvm_unreachable("Unknown register class");
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}
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unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
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unsigned maxUsed = hwReg + width - 1;
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if (isSGPR) {
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MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
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} else {
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MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
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}
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}
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}
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}
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if (VCCUsed)
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MaxSGPR += 2;
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if (FlatUsed)
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MaxSGPR += 2;
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// We found the maximum register index. They start at 0, so add one to get the
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// number of registers.
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ProgInfo.NumVGPR = MaxVGPR + 1;
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ProgInfo.NumSGPR = MaxSGPR + 1;
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// Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
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// register.
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ProgInfo.FloatMode = getFPMode(MF);
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// XXX: Not quite sure what this does, but sc seems to unset this.
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ProgInfo.IEEEMode = 0;
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// Do not clamp NAN to 0.
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ProgInfo.DX10Clamp = 0;
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const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
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ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
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ProgInfo.FlatUsed = FlatUsed;
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ProgInfo.VCCUsed = VCCUsed;
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ProgInfo.CodeLen = CodeSize;
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}
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void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
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const SIProgramInfo &KernelInfo) {
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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unsigned RsrcReg;
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switch (MFI->getShaderType()) {
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default: // Fall through
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case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
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case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
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case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
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case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
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}
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unsigned LDSAlignShift;
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if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
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// LDS is allocated in 64 dword blocks.
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LDSAlignShift = 8;
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} else {
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// LDS is allocated in 128 dword blocks.
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LDSAlignShift = 9;
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}
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unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
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MFI->getMaximumWorkGroupSize(MF);
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unsigned LDSBlocks =
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RoundUpToAlignment(MFI->LDSSize + LDSSpillSize,
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1 << LDSAlignShift) >> LDSAlignShift;
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// Scratch is allocated in 256 dword blocks.
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unsigned ScratchAlignShift = 10;
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// We need to program the hardware with the amount of scratch memory that
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// is used by the entire wave. KernelInfo.ScratchSize is the amount of
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// scratch memory used per thread.
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unsigned ScratchBlocks =
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RoundUpToAlignment(KernelInfo.ScratchSize * STM.getWavefrontSize(),
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1 << ScratchAlignShift) >> ScratchAlignShift;
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unsigned VGPRBlocks = (KernelInfo.NumVGPR - 1) / 4;
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unsigned SGPRBlocks = (KernelInfo.NumSGPR - 1) / 8;
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if (MFI->getShaderType() == ShaderType::COMPUTE) {
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OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
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const uint32_t ComputePGMRSrc1 =
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S_00B848_VGPRS(VGPRBlocks) |
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S_00B848_SGPRS(SGPRBlocks) |
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S_00B848_PRIORITY(KernelInfo.Priority) |
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S_00B848_FLOAT_MODE(KernelInfo.FloatMode) |
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S_00B848_PRIV(KernelInfo.Priv) |
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S_00B848_DX10_CLAMP(KernelInfo.DX10Clamp) |
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S_00B848_IEEE_MODE(KernelInfo.DebugMode) |
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S_00B848_IEEE_MODE(KernelInfo.IEEEMode);
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OutStreamer.EmitIntValue(ComputePGMRSrc1, 4);
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OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
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const uint32_t ComputePGMRSrc2 =
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S_00B84C_LDS_SIZE(LDSBlocks) |
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S_00B02C_SCRATCH_EN(ScratchBlocks > 0);
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OutStreamer.EmitIntValue(ComputePGMRSrc2, 4);
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OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
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OutStreamer.EmitIntValue(S_00B860_WAVESIZE(ScratchBlocks), 4);
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// TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
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// 0" comment but I don't see a corresponding field in the register spec.
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} else {
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OutStreamer.EmitIntValue(RsrcReg, 4);
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OutStreamer.EmitIntValue(S_00B028_VGPRS(VGPRBlocks) |
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S_00B028_SGPRS(SGPRBlocks), 4);
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}
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if (MFI->getShaderType() == ShaderType::PIXEL) {
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OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
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OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
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OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
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OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
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|
}
|
|
}
|