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https://github.com/c64scene-ar/llvm-6502.git
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02d711b93e
instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
672 B
LLVM
25 lines
672 B
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep xswd %t1.s | count 1
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; RUN: grep shufb %t1.s | count 2
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; RUN: grep cg %t1.s | count 1
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; RUN: grep addx %t1.s | count 1
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; ModuleID = 'stores.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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define i64 @sext_i64_i32(i32 %a) nounwind {
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%1 = sext i32 %a to i64
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ret i64 %1
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}
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define i64 @zext_i64_i32(i32 %a) nounwind {
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%1 = zext i32 %a to i64
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ret i64 %1
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}
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define i64 @add_i64(i64 %a, i64 %b) nounwind {
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%1 = add i64 %a, %b
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ret i64 %1
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}
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