Nadav Rotem d6fb53adb1 On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized ... register. In most cases we actually compare or select YMM-sized registers and mixing the two types creates horrible code. This commit optimizes some of the transition sequences. PR14657. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8		2012-12-27 08:15:45 +00:00
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ARM	Revert "Adding support for llvm.arm.neon.vaddl[su].* and"	2012-12-20 21:09:38 +00:00
CPP
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon
MBlaze
Mips	Add test case for r170674	2012-12-21 00:55:10 +00:00
MSP430
NVPTX
PowerPC	Loosen scheduling restrictions on the PPC dcbt intrinsic	2012-12-25 18:51:18 +00:00
R600	R600: Expand vec4 INT <-> FP conversions	2012-12-21 16:33:24 +00:00
SI
SPARC
Thumb
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized	2012-12-27 08:15:45 +00:00
XCore