Nadav Rotem d6fb53adb1 On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized ... register. In most cases we actually compare or select YMM-sized registers and mixing the two types creates horrible code. This commit optimizes some of the transition sequences. PR14657. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8		2012-12-27 08:15:45 +00:00
..
ARM	Revert "Adding support for llvm.arm.neon.vaddl[su].* and"	2012-12-20 21:09:38 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon	In hexagon convertToHardwareLoop, don't deref end() iterator	2012-12-07 21:03:15 +00:00
MBlaze
Mips	Add test case for r170674	2012-12-21 00:55:10 +00:00
MSP430	Add support for varargs functions for msp430.	2012-11-21 17:28:27 +00:00
NVPTX	[NVPTX] Fix crash with unnamed struct arguments	2012-12-05 20:50:28 +00:00
PowerPC	Loosen scheduling restrictions on the PPC dcbt intrinsic	2012-12-25 18:51:18 +00:00
R600	R600: Expand vec4 INT <-> FP conversions	2012-12-21 16:33:24 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Use TargetTransformInfo to control switch-to-lookup table transformation	2012-10-30 11:23:25 +00:00
Thumb	Use the 'count' attribute to calculate the upper bound of an array.	2012-12-04 21:34:03 +00:00
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized	2012-12-27 08:15:45 +00:00
XCore	Fix handling of aliases to functions.	2012-11-16 21:12:38 +00:00