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6824f127f9
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
207 lines
8.2 KiB
C++
207 lines
8.2 KiB
C++
//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
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#define LLVM_TARGET_SYSTEMZINSTRINFO_H
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#include "SystemZ.h"
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#include "SystemZRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "SystemZGenInstrInfo.inc"
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namespace llvm {
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class SystemZTargetMachine;
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namespace SystemZII {
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enum {
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// See comments in SystemZInstrFormats.td.
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SimpleBDXLoad = (1 << 0),
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SimpleBDXStore = (1 << 1),
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Has20BitOffset = (1 << 2),
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HasIndex = (1 << 3),
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Is128Bit = (1 << 4),
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AccessSizeMask = (31 << 5),
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AccessSizeShift = 5
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};
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static inline unsigned getAccessSize(unsigned int Flags) {
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return (Flags & AccessSizeMask) >> AccessSizeShift;
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}
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// SystemZ MachineOperand target flags.
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enum {
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// Masks out the bits for the access model.
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MO_SYMBOL_MODIFIER = (1 << 0),
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// @GOT (aka @GOTENT)
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MO_GOT = (1 << 0)
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};
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// Classifies a branch.
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enum BranchType {
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// An instruction that branches on the current value of CC.
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BranchNormal,
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// An instruction that peforms a 32-bit signed comparison and branches
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// on the result.
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BranchC,
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// An instruction that peforms a 64-bit signed comparison and branches
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// on the result.
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BranchCG
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};
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// Information about a branch instruction.
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struct Branch {
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// The type of the branch.
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BranchType Type;
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// CCMASK_<N> is set if CC might be equal to N.
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unsigned CCValid;
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// CCMASK_<N> is set if the branch should be taken when CC == N.
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unsigned CCMask;
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// The target of the branch.
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const MachineOperand *Target;
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Branch(BranchType type, unsigned ccValid, unsigned ccMask,
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const MachineOperand *target)
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: Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
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};
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}
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class SystemZInstrInfo : public SystemZGenInstrInfo {
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const SystemZRegisterInfo RI;
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SystemZTargetMachine &TM;
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void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
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public:
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explicit SystemZInstrInfo(SystemZTargetMachine &TM);
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// Override TargetInstrInfo.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const LLVM_OVERRIDE;
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const LLVM_OVERRIDE;
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virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
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int &SrcFrameIndex) const LLVM_OVERRIDE;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const LLVM_OVERRIDE;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const LLVM_OVERRIDE;
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virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const
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LLVM_OVERRIDE;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumCyclesT,
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unsigned ExtraPredCyclesT,
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MachineBasicBlock &FMBB,
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unsigned NumCyclesF,
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unsigned ExtraPredCyclesF,
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const BranchProbability &Probability) const
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LLVM_OVERRIDE;
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virtual bool
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const
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LLVM_OVERRIDE;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const LLVM_OVERRIDE;
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virtual void
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storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
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virtual void
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loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
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virtual MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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virtual MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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virtual MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const;
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virtual bool
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expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
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virtual bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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LLVM_OVERRIDE;
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// Return the SystemZRegisterInfo, which this class owns.
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const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
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// Return the size in bytes of MI.
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uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
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// Return true if MI is a conditional or unconditional branch.
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// When returning true, set Cond to the mask of condition-code
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// values on which the instruction will branch, and set Target
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// to the operand that contains the branch target. This target
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// can be a register or a basic block.
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SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
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// Get the load and store opcodes for a given register class.
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void getLoadStoreOpcodes(const TargetRegisterClass *RC,
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unsigned &LoadOpcode, unsigned &StoreOpcode) const;
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// Opcode is the opcode of an instruction that has an address operand,
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// and the caller wants to perform that instruction's operation on an
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// address that has displacement Offset. Return the opcode of a suitable
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// instruction (which might be Opcode itself) or 0 if no such instruction
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// exists.
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unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
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// Return true if ROTATE AND ... SELECTED BITS can be used to select bits
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// Mask of the R2 operand, given that only the low BitSize bits of Mask are
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// significant. Set Start and End to the I3 and I4 operands if so.
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bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
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unsigned &Start, unsigned &End) const;
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// If Opcode is a COMPARE opcode for which an associated COMPARE AND
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// BRANCH exists, return the opcode for the latter, otherwise return 0.
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// MI, if nonnull, is the compare instruction.
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unsigned getCompareAndBranch(unsigned Opcode,
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const MachineInstr *MI = 0) const;
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// Emit code before MBBI in MI to move immediate value Value into
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// physical register Reg.
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void loadImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned Reg, uint64_t Value) const;
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};
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} // end namespace llvm
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#endif
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