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https://github.com/c64scene-ar/llvm-6502.git
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6215f78195
This patch makes the ARM backend transform 3 operand instructions such as 'adds/subs' to the 2 operand version of the same instruction if the first two register operands are the same. Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'. Currently for some instructions such as 'adds' if you try to assemble 'adds r0, r0, #8' for thumb v6m the assembler would throw an error message because the immediate cannot be encoded using 3 bits. The backend should be smart enough to transform the instruction to 'adds r0, #8', which allows for larger immediate constants. Patch by Ranjeet Singh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218521 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.5 KiB
ArmAsm
53 lines
1.5 KiB
ArmAsm
@ RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s
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adds r0, r0, #8
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@ CHECK: adds r0, #8 @ encoding: [0x08,0x30]
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adds r0, r0, r0
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@ CHECK: adds r0, r0, r0 @ encoding: [0x00,0x18]
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add r0, r0, r8
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@ CHECK: add r0, r8 @ encoding: [0x40,0x44]
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add sp, sp, r0
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@ CHECK: add sp, r0 @ encoding: [0x85,0x44]
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add r0, r0, r1
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@ CHECK: add r0, r1 @ encoding: [0x08,0x44]
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add r2, r2, r3
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@ CHECK: add r2, r3 @ encoding: [0x1a,0x44]
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subs r0, r0, r0
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@ CHECK: subs r0, r0, r0 @ encoding: [0x00,0x1a]
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ands r0, r0, r1
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@ CHECK: ands r0, r1 @ encoding: [0x08,0x40]
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eors r0, r0, r1
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@ CHECK: eors r0, r1 @ encoding: [0x48,0x40]
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lsls r0, r0, r1
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@ CHECK: lsls r0, r1 @ encoding: [0x88,0x40]
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lsrs r0, r0, r1
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@ CHECK: lsrs r0, r1 @ encoding: [0xc8,0x40]
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asrs r0, r0, r1
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@ CHECK: asrs r0, r1 @ encoding: [0x08,0x41]
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adcs r0, r0, r1
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@ CHECK: adcs r0, r1 @ encoding: [0x48,0x41]
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sbcs r0, r0, r1
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@ CHECK: sbcs r0, r1 @ encoding: [0x88,0x41]
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rors r0, r0, r1
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@ CHECK: rors r0, r1 @ encoding: [0xc8,0x41]
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orrs r0, r0, r1
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@ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
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bics r0, r0, r1
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@ CHECK: bics r0, r1 @ encoding: [0x88,0x43]
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