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c4af4638df
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
3.4 KiB
LLVM
113 lines
3.4 KiB
LLVM
; RUN: llc < %s -march=arm | FileCheck -check-prefix=ARM %s
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; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s
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; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s
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; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified.
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%struct.Foo = type { i8* }
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; ARM: foo
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; THUMB: foo
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; T2: foo
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define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 {
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entry:
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%scevgep = getelementptr %struct.Foo* %this, i32 1
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br label %tailrecurse
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tailrecurse: ; preds = %sw.bb, %entry
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%lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ]
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%lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ]
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%acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ]
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%lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8**
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%scevgep5 = getelementptr i8** %lsr.iv24, i32 -1
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%tmp2 = load i8** %scevgep5
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%0 = ptrtoint i8* %tmp2 to i32
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; ARM: ands r12, r12, #3
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; ARM-NEXT: beq
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; THUMB: movs r5, #3
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; THUMB-NEXT: ands r5, r4
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; THUMB-NEXT: cmp r5, #0
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; THUMB-NEXT: beq
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; T2: ands r12, r12, #3
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; T2-NEXT: beq
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%and = and i32 %0, 3
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%tst = icmp eq i32 %and, 0
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br i1 %tst, label %sw.bb, label %tailrecurse.switch
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tailrecurse.switch: ; preds = %tailrecurse
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switch i32 %and, label %sw.epilog [
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i32 1, label %sw.bb
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i32 3, label %sw.bb6
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i32 2, label %sw.bb8
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]
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sw.bb: ; preds = %tailrecurse.switch, %tailrecurse
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%shl = shl i32 %acc.tr, 1
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%or = or i32 %and, %shl
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%lsr.iv.next = add i32 %lsr.iv, 1
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%scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1
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br label %tailrecurse
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sw.bb6: ; preds = %tailrecurse.switch
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ret %struct.Foo* %lsr.iv2
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sw.bb8: ; preds = %tailrecurse.switch
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%tmp1 = add i32 %acc.tr, %lsr.iv
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%add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1
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ret %struct.Foo* %add.ptr11
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sw.epilog: ; preds = %tailrecurse.switch
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ret %struct.Foo* undef
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}
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; Another test that exercises the AND/TST peephole optimization and also
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; generates a predicated ANDS instruction. Check that the predicate is printed
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; after the "S" modifier on the instruction.
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%struct.S = type { i8* (i8*)*, [1 x i8] }
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; ARM: bar
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; THUMB: bar
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; T2: bar
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define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
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entry:
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%0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0
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%1 = load i8* %0, align 1
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%2 = zext i8 %1 to i32
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; ARM: ands
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; THUMB: ands
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; T2: ands
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%3 = and i32 %2, 112
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%4 = icmp eq i32 %3, 0
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br i1 %4, label %return, label %bb
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bb: ; preds = %entry
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%5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0
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%6 = load i8* %5, align 1
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%7 = zext i8 %6 to i32
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; ARM: andsne
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; THUMB: ands
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; T2: andsne
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%8 = and i32 %7, 112
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%9 = icmp eq i32 %8, 0
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br i1 %9, label %return, label %bb2
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bb2: ; preds = %bb
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%10 = icmp eq i32 %3, 16
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%11 = icmp eq i32 %8, 16
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%or.cond = or i1 %10, %11
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br i1 %or.cond, label %bb4, label %return
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bb4: ; preds = %bb2
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%12 = ptrtoint %struct.S* %x to i32
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%phitmp = trunc i32 %12 to i8
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ret i8 %phitmp
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return: ; preds = %bb2, %bb, %entry
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ret i8 1
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}
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