mirror of
https://github.com/c64scene-ar/llvm-6502.git
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86c6d80a7a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
4.1 KiB
LLVM
94 lines
4.1 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vld1dupi8(i8* %A) nounwind {
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;CHECK: vld1dupi8:
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;Check the (default) alignment value.
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;CHECK: vld1.8 {d16[]}, [r0]
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%tmp1 = load i8* %A, align 8
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%tmp2 = insertelement <8 x i8> undef, i8 %tmp1, i32 0
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%tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <8 x i32> zeroinitializer
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vld1dupi16(i16* %A) nounwind {
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;CHECK: vld1dupi16:
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vld1.16 {d16[]}, [r0, :16]
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%tmp1 = load i16* %A, align 8
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%tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0
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%tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vld1dupi32(i32* %A) nounwind {
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;CHECK: vld1dupi32:
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;Check the alignment value. Max for this instruction is 32 bits:
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;CHECK: vld1.32 {d16[]}, [r0, :32]
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%tmp1 = load i32* %A, align 8
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%tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
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%tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
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;CHECK: vld1dupQi8:
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;Check the (default) alignment value.
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;CHECK: vld1.8 {d16[], d17[]}, [r0]
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%tmp1 = load i8* %A, align 8
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%tmp2 = insertelement <16 x i8> undef, i8 %tmp1, i32 0
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%tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <16 x i32> zeroinitializer
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ret <16 x i8> %tmp3
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}
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%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
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%struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }
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define <8 x i8> @vld2dupi8(i8* %A) nounwind {
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;CHECK: vld2dupi8:
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;Check the (default) alignment value.
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;CHECK: vld2.8 {d16[], d17[]}, [r0]
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%tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
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%tmp1 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 0
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 1
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%tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <8 x i32> zeroinitializer
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%tmp5 = add <8 x i8> %tmp2, %tmp4
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ret <8 x i8> %tmp5
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}
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define <2 x i32> @vld2dupi32(i32* %A) nounwind {
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;CHECK: vld2dupi32:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vld2.32 {d16[], d17[]}, [r0, :64]
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%tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i32* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
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%tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp3 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 1
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%tmp4 = shufflevector <2 x i32> %tmp3, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp5 = add <2 x i32> %tmp2, %tmp4
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ret <2 x i32> %tmp5
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}
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declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly
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declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i32*, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
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%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
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define <4 x i16> @vld3dupi16(i16* %A) nounwind {
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;CHECK: vld3dupi16:
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;Check the (default) alignment value. VLD3 does not support alignment.
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;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
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%tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
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%tmp1 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 0
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
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%tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 1
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%tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer
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%tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 2
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%tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer
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%tmp7 = add <4 x i16> %tmp2, %tmp4
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%tmp8 = add <4 x i16> %tmp7, %tmp6
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ret <4 x i16> %tmp8
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}
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declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
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